This has sprung from a desire to have "better" synchronous triggers. The xml configuration files, contains a "delay" for RX and TX. As it is, these delays are all set to 0 and the triggers are not "as" synchronous as they might be since the time it takes for a trigger to travel to BOC to module are different. This is a combination of the length of the patch fibres and the length of the fibre on the barrels. Tony Weidberg has provided a very detailed list of all the fibre lengths of all the different harness types on the barrels (there are 46 different types of "fibre stacks" evidently).
I am planning on writing a script (much like the script that writes the MURs) that figures out which fibre-stack type an MUR is and replaces the delays with the appropriate delay. I am putting some information on this here as I learn things...
Things to consider:
- Light takes 5ns/m to travel down a fibre.
- Fibre-lengths on the barrels: Known to mm-accuracy from file provided by Tony Weidberg.
- Fibre-lengths from BOC to barrel: Not well known. Assumed to be equal for all at OxfordSetup. From the ATLASpit to the BOC, the fibre lenghts are approximately 90meters. The error on this is supposed to be around 1m. These will be measured to some good accuracy before they are used.
- In actual physics running: the TOF for a particle from ID to module. This delay will be different for each barrel and module position, but otherwise same in phi.
The BOC has two TxDelay registers: Fine delay register and coarse delay register and one RxDelay register.
Scripts you might like to use
(First source an appropriate setup scripts, and them if in combined running overwrite the TDAQ_PARTITION environment variable with the name of the central partition.
To set TxDelays? based on fibre lengths:
runjava sctutils/SetTxDelays <options>
To add or subtract an integer number of bunch crossings to the Tx Coarse Delay
runjava sctutils/SetBOCDelay 3 # GOOD .. increased delay by 3 runjava sctutils/SetBOCDelay -2 # GOOD .. decreases delay by 2 runjava sctutils/SetBOCDelay +2 # BAD -- doesn't like "+" !
Links
[BOC_Timing_Overview.pdf] has some interesting ideas.
LTP = Local Trigger processor is the source of the external triggering.