Hardware
For this, the LTP VME crate is used as well as a TDC and an ADC.- [LTP], the Local Timing Processor provides the L1 and BC signals.
- CORBO, [RCB 8047] is used as a counter for L1s and the busy.
- TDC, Time to Digital Converter, [CAEN V775], has 12 bit resolution and the Full Scale Range can be selected via VME from 140 ns to 1.2 microsecs with 8 bit resolution. This means that the smallest time difference we can measure with this TDC is 35 psecs.
- ADC, Analog to Digital Converter, [CAEN V792], is a charge integrating ADC (QDC) and has 12 bit resolution and the input range is from 0 to 400 pC with 50 Ohm impedance.
Software
From the TileCal? detector CVS from TDAQ, get the distribution. This uses RCD.This distribution is now on /daqsoft/sct/TimingInfo?/detectors/Tile/
You have to be on the SBC to run the test program. So on lnxpool17, in the directory: /daqsoft/sct/TimingInfo?/detectors/Tile/TileVMEboards?/i686-slc3-gcc323-opt
The ADC replies when you do:
./v792_test 0x00200000 1
And the TDC replies when you do:
./v775_test 0x00100000 1
The dip switch on the corbo is set to 0x400000 -- but it replies to 0x600000 from vmescan!
./corbo_test 0x600000 1 30000 15
vmeconfig -a ~sr1daq/temp.cfg
SctRodDaq
What is needed from the SctRodDaq point of view?
Notes
Notes from 2006/02/28
Bilge and Chris tried to get the Corbo+TDQ+QDC modules running in the cosmics environment.
Chris (and also Bilge?) running as sr1daq on srsctdaq1 sourcing /home/sr1daq/setup.SCT.sh which sets TDAQ_DB_DATA to /daqsoft/combined/partitions/part_SCT.xml which is not quite what we need as we use /daqsoft/combined/partitions/part_SCT_withCorboTDCQDCSegment.xml instead. This brings in the segment defined in daqsoft/combined/segments/SctCorboTDCQDC?.data.xml which is the one we want to bring in to play.
Still, it's getting closer. Need to find out why the Corbo is timing out.
Notes from 2006/03/01
Corrected the CORBO channel. Even though the CORBO manual says that the channel counting starts from 1, in software it starts from 0.
The dataout is the crucial thing that links things. The dataout from the Corbo segment is from TCP and of RODfragment type. It does not let us send this directly to the EB as a ROD fragment -- since the EB gets a ROS fragment as well. Then one needs to wrap it up on the ROS... into a ROS fragment. If we try to wrap up this ROD fragment with other ROD fragments coming from the ROD, we get an error saying they are from different type of modules!
So the thing to do is to have a new ROSsegment, building a new ROSfragment and passing that on to the EB....
March 08 Notes
The above solution works. There is a new Sub-detector fragment, which identifies itself as a TDAQ-Beam-Crate, which contains one ROS fragment which contains one ROD fragment which then contains two sub-ROD fragments, one for the ADC and one for the TDC.
The problem: errors in the first 7 events... This is because the trigger is the same for all modules and the new fragment is built faster (150ns or so faster? ) than the ROD-fragments from the modules...
When I changed the trigger so now that LTP controls the whole chain, the TDC exerts a constant BUSY and so no triggers are issued. This is now the new problem!
March 21 Notes
Yesterday the LTP crate and the corresponding NIM crate for trigger logic was moved over to where the cosmics NIM crates are. This should help get the scintillator signals into the TDC/ADC.
March 23 Notes
Bilge's summary e-mail:
Here is a brief summary of what we found out in the last few days with
Dave.
The L1ID problem was solved earlier when Peter was here by issuing an ECR
at the end of the "start" state transition.
The problem then was that occasionaly an BCR (orbit) signal coincided/ was
close to an L1A and then we got "timeout errors" in that event. This event
was followed by events with L1 errors.
It seems that the orbit signal is 1microsecond wide and the only
solutiono seems to be that we veto triggers during the whole duration of
that. We originally thought that suppressing the L1As within 6-8BCs
of the orbit leading edge would be enough but this was proven not to be
the case.
The other problem of the first seven fragments of the TDC/ADC missing was
probably due to getting the trigger from the "L1A out" of the LTP. Getting
it from the "out" of the TTCvi solves this problem. Evidently, it takes a
while for the TTCvi to "wake up" and pass on triggers?
The problem that was then left that either you would have the SCT fragment
or the TDC/ADC fragment in the bytestream but not both. The cause seems
to be "the Extended L1ID" which in its top two bits uses the ECR count.
When we use a TIM issued ECR to fix the L1ID at the "start" state
transition, the first L1ID is 0x1000000 where as the TDC/ADC fragment gets
its L1ID from the Corbo module and the first L1ID is 0x0. The fix now in
place is to "by hand" add a bit into the TDC/ADC fragment. Clearly, this
is a hack...
This also sheds some light as to why we could not run the TRT and the SCT
together after I had done an ECR by hand. Before the ECR, the eventbuilder
happily accepted building events but afterwards built events with
only with the TRT fragment in it and issued a lot of errors about the SCT
L1ID.
What needs to be done is that the ECR needs to be issued globally from the
Master LTP. Otherwise, we will not be syncronized with the TRT. Ideally,
we would use another Corbo channel to count the ECRs and to build the
extended L1ID for the TDC/ADC segment, which I think is doable.
Work on this continues, but I think there is progress...
Run 2198 has good data with both the SCT and the TDC/ADC fragment in it.