This suite of programs requires ~22MByte of disk space (after unzipping), and requires LabView version 5.0 or higher to be installed.
I recommend a fast PC, as the DAQ program incorporates event analysis and histogramming - max event rate is ~20Hz on our 450MHz PIII machine, ~10Hz on our older 266MHz machine with full event processing enabled.

It comprises 4 main programs:

• sctTool.vi - interactive facility to set up and trigger the chip, ideal for debugging, observing the data train, setting up strobes, signal "hunting" (eg

T1 scanning to search the pipeline for a source signal) etc
• runDAQ.vi - full DAQ system, with event processing, file management, histogram saving etc
• readHistos.vi - to inspect and analyse saved histograms
• readData.vi - to run the event processor on saved raw data files, as if taking "real" data

Run winzip on the above zip file. I recommend you install into the default root directory, ie in C:\sct128

If, for whatever reason, you need to install in a different root directory, you have to do the following:

1. edit the siconfig.txt file (supplied in C:\sct128) to the actually directories used (the siconfig.txt file defines where to
store raw data files and histo files etc, where the run number is stored and so on).
2. Edit the GetLocalConfig.vi file (supplied in C:\sct128\daq\) and edit the correct location of the siconfig.txt file
 

Hardware
For sctTool.vi, you only need

• seqsi

• seqsi
• corbo
• sirocco - runs with old sirocco as well as new VFAS
• tdc (optional - can switch this off by s/w)

VXI Configuration

Use the VXI Resource Editor (from the ni-vxi Start menu) to invoke the "Non-VXI Device Configuration Editor", and set
the "PseudoLAs" of the following modules accordingly:

seqsi 281
corbo 282
sirocco 311
tdc 284

If you don't want to do this, for whatever reason, edit the C:\sct128\vxi\GetVXIMap.vi, and edit the PseudoLAs in the case diagram to the
values actually used in your crate.

Cabling

You must set up the following cabling. You can change the software to modify the cabling at your own risk.
 

SEQSI             Pin Nos             ECL/NIM/ECL         Pin Number of J1            Description
Chan               SEQSI PL2        LRS4616 Chan No   Connector on sct board   (output(s) used from ecl/nim/ecl)
(starts from 0)  (starts from 1)    (starts from 1)            (starts from 1)

clock                46,47                 1                              1,2                                 Clock - ecl to chip, nim  to logic
4                         9,10                3                              5,6                                  Reset - ecl to chip
5                       11,12                4                              7,8                                  Polarity - ecl to chip
6                       13,14                5                              9,10                                Address - ecl to chip
7                       15,16                6                            11,12                                tstenable - ecl to chip, not used?
8                       17,18                7                            13,14                                command - ecl to chip
9                       19,20                8                            15,16                                singread 0- ecl to chip
10                     21,22                9                            17,18                                muxtstenable - ecl to chip, not used?
11                     23,24              10                              n/a                                   sirocco strobe (sync stop) -  nim to logic
12                     25,26              11                              n/a                                   not used
13                     27,28              12                              n/a                                   trsynchro - not used (historical)
14                     29,30              13                              n/a                                   sofware trigger - nim to logic
15                     31,32              14                              n/a                                   enable source trigs - nim to logic
16                     33,34              15                              n/a                                   sirocco gate - nim to logic
17                     35,36              16                              n/a                                   TDC stop - ECL to TDC module
30 (nim o/p)      n/a                   n/a                             n/a                                   sirocco strobe (sync start) to nim logic

NIM logic
A very (very) rough hand-drawn logic diagram should be visible here: