BOC_model3.html @15:18 on 9-Feb-00

BOC Essential Model

<Maurice Goodrick> (University of Cambridge, Cavendish Labs)

Notes and Conventions

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** Notes in RED are issues to be noted or discussed **


This document is a preliminary and incomplete draft of the Essential Model of the SCT BOC Module and its interfaces. Feedback is welcome.




The BOC (or Back Of Crate) module is a component of the Atlas Silicon Central Tracker - Off Detector Electronics: it is the primary data and control interface between the modules (both Strip and Pixel, and in both the Barrel and the End-Caps). As such, it performs the following core functions:

A number of related and ancillary tasks are also performed, such as:


The format will be a single width 9U VME64 transition module of depth 240mm.

Each ROD in the crate will have a BOC sitting behind it in the transition-module (or "back-of-crate") location.

BOC will have no connection to P1/J1, and will have no VME functionality.

All control operations on BOC are achieved through its partner ROD using the Set-Up Bus


A version is planned that matches the needs of the Pixel modules: this may imply different numbers of data and control streams, and a de-multiplexing of the 80MHz data streams into pairs of 40 MHz streams.


Prototypes may have different formats (in particular, reduced numbers of streams) according to the available components. There may also be differences in function.


A complete description of Atlas SCT Off Detector Electronics is available at Atlas_Off-Detector>>



Signal levels:

TTL signals originating on BOC are from drivers running from a +3.3V supply.

TTL signals received by BOC should preferably be from drivers running from a +3.3V supply.

PECL5V signals originating on BOC come from ECL drivers running on a +5V supply: they are balanced, and have pull-down resistors (but no termination resistors) on-board.

PECL5V signals received by BOC should come from ECL drivers running on a +5V supply: they should be balanced. They are terminated on BOC, but have no pull-down resistors.



  • < SLD[31:0]

32 bit data word


  • < SL_CLK

S-Link Data-In clock



data word write enable


  • > X-OFF

Link Full (ROD stops in 2 data words)


  • < SL-RESET

Reset S-Link


  • < SL-TEST

Test pattern generation


  • SL-UD[3:0]

To be decided


  • > SL-BAD

Link is down




The detailed definition of the SCT Off-Detector Crate Backplane and Slot Usage is given in Backplane-and-Slots (.ps) >>

The realisation of this in the BOC schematics is shown in rp2_rp3.pdf >

The Set-Up Bus interface and the State Maps for the handshake for transfers across it are shown in setupbus.pdf > . The version shown is correct, but will be augmented shortly.

The Top Level Address Map for the Set-Up Bus is shown in add_map_top.pdf >. The fine structure is shown in add_map_detail.pdf >.

The BOC Timing document, BOC_Timing_Overview.pdf >, shows the provision for adjusting the phase of the incoming data streams with respect to the ROD clock, and the way in which it can be used to accurately measure the relative timing of clock and control signals arriving at each detector module with respect to its neighbour. This is an early version of this document which gives an overview of hardware implementations and how they would operate: BOC0 implements one of these architectures.

The Pixel Modules have special requirements:

BOC0 will not adjust the stream count to optimise for Pixels. It will also make a trial provision to split a small number of 80Mbaud data streams into pairs of 40Mbaud streams to be passed to the ROD.

BOC1 will aim to fully provide for Pixel modules. The differences in numerology will probably be accomplished by partial population of a standard BOC module.

A document will be added to explain this splitting of 80 Mbaud streams. BOC_Pixels.pdf (not yet valid) >


BOC0 differences:

Most of the differences between BOC0 and BOC1 appear in the text above. The following notes are also relevant: