TimDefine.h

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//File: TimDefine.h

#ifndef SCTPIXELROD_TIMDEFINE_H
#define SCTPIXELROD_TIMDEFINE_H

namespace SctPixelRod {

#include "processor.h"


enum TimTimingSCT {
     TIM_L1A_DEADTIME =  3,
     TIM_ECR_DEADTIME =  7,
     TIM_BCR_DEADTIME =  7,
     TIM_CAL_DEADTIME = 27,
     TIM_BCID_OFFSET  =  6
};

const INT32 TIM_L1ID_FIRST = 0; 

const INT32 TIM_SEQ_SIZE = 0x4000; 
const INT32 TIM_SEQ_ADDR = 0x8000; 


enum TimRegister {
     TIM_REG_ENABLES      = 0x00,
     TIM_REG_COMMAND      = 0x02,
     TIM_REG_BURST_COUNT  = 0x04,
     TIM_REG_FREQUENCY    = 0x06,
     TIM_REG_WINDOW       = 0x08,
     TIM_REG_DELAY        = 0x0A,
     TIM_REG_STATUS       = 0x0C,
     TIM_REG_FIFO_STATUS  = 0x0E,
     TIM_REG_TRIGGER_IDLO = 0x10,
     TIM_REG_TRIGGER_IDHI = 0x12,
     TIM_REG_TRIGGER_BCID = 0x14,
     TIM_REG_TRIGGER_TYPE = 0x16,
     TIM_REG_RUN_ENABLES  = 0x18,
     TIM_REG_SEQ_CONTROL  = 0x1A,
     TIM_REG_SEQ_END      = 0x1C,
     TIM_REG_ROD_MASK     = 0x1E,
     TIM_REG_ROD_BUSY     = 0x20,
     TIM_REG_ROD_LATCH    = 0x22,
     TIM_REG_ROD_MONITOR  = 0x24,
     TIM_REG_TTC_DATA     = 0x26,
     TIM_REG_TTC_SELECT   = 0x28,
     TIM_REG_TTC_BCID     = 0x2A,
     TIM_REG_TTC_RX       = 0x2C,
     TIM_REG_TTC_STATUS   = 0x2E,
     TIM_REG_OUTPUT       = 0x30,
     TIM_REG_TIM_ID       = 0x32
};


enum TimBitEnables {
     TIM_BIT_EN_INT_TRIG = 0x0002,  
     TIM_BIT_EN_INT_ECR  = 0x0004,  
     TIM_BIT_EN_INT_BCR  = 0x0008,  
     TIM_BIT_EN_RANDOM   = 0x0010,  
     TIM_BIT_EN_INT_FER  = 0x0020,  
     TIM_BIT_EN_WINDOW   = 0x0040,  
     TIM_BIT_EN_INT_BUSY = 0x0080,  

     TIM_BIT_EN_EXT_CLK  = 0x0100,  
     TIM_BIT_EN_EXT_TRIG = 0x0200,  
     TIM_BIT_EN_EXT_ECR  = 0x0400,  
     TIM_BIT_EN_EXT_BCR  = 0x0800,  
     TIM_BIT_EN_EXT_CAL  = 0x1000,  
     TIM_BIT_EN_EXT_FER  = 0x2000,  
     TIM_BIT_EN_EXT_SEQ  = 0x4000,  
     TIM_BIT_EN_EXT_BUSY = 0x8000   
};

enum TimMaskFrequency {
     TIM_MASK_TRIG_100_KHZ = 0x0006,
     TIM_MASK_TRIG_10_0KHZ = 0x000E,
     TIM_MASK_TRIG_1_00KHZ = 0x0016,
     TIM_MASK_TRIG_0_10KHZ = 0x001E,

     TIM_MASK_FER_10_00HZ  = 0x0600,
     TIM_MASK_FER_1_000HZ  = 0x0E00,
     TIM_MASK_FER_0_100HZ  = 0x1600,
     TIM_MASK_FER_0_010HZ  = 0x1E00
};
enum TimBitBackplane {
     TIM_L1A = 0x01,       
     TIM_ECR = 0x02,       
     TIM_BCR = 0x04,       
     TIM_CAL = 0x08,       
     TIM_SID = 0x10,       
     TIM_STT = 0x20,       
     TIM_CMD = 0xCF,       
     TIM_RES = 0xC0,       
     TIM_FER = 0x40,       
     TIM_SPA = 0x80,       
     TIM_TRG = 0x31        
};
enum TimBitCommand {
     TIM_VTRG = 0x02,      
     TIM_VECR = 0x04,      
     TIM_VBCR = 0x08,      
     TIM_VCAL = 0x10,      
     TIM_VFER = 0x20,      
     TIM_VSPA = 0x40,      

     TIM_BIT_VRESET = 0x8000
};

enum TimBitRunEnables {
     TIM_BIT_EN_ID   = 0x0200,
     TIM_BIT_EN_TYPE = 0x0400
};

enum TimBitSeqControl {
     TIM_BIT_SEQ_EN_ALL = 0x00FF,
     TIM_BIT_SEQ_RESET  = 0x0200,
     TIM_BIT_SEQ_GO     = 0x0400,
     TIM_BIT_EN_CYCLIC  = 0x0800
};

} // End namespace SctPixelRod

#endif // SCTPIXELROD_TIMDEFINE_H

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