interModule.cxx

{
#include "../extraScans.h"
// Inter module timing?
TScanDef inter;

inter.trigsPerBurst = 10;
inter.trigSequence.singleL1A();

tapi.modifyBOCParam(SCT_SCAN_BOC_VRN_FINE, 127);

// Put all modules in clk/2 mode
tapi.modifyABCDVar(ST_FEEDTHROUGH, 0.0);
tapi.setABCDModules(0);
tapi.sendABCDModules(0);

// {
//   // VREG 24 -> 0
//   tapi.modifyBOCParam(SCT_SCAN_BOC_V1_PHASE, 0);
//   inter.configure(SCT_SCAN_BOC_V0_PHASE, 24, 0, -1);

//   // Sample at clock/2 rate
//   tapi.doRawScan(raw, 1, 768, false, true);
//   tapi.awaitScan();
// }

// {
//   // VREG 24->48
//   tapi.modifyBOCParam(SCT_SCAN_BOC_V1_PHASE, 24);
//   inter.configure(SCT_SCAN_BOC_V0_PHASE, 0, 24, 1);

//   // Sample at clock/2 rate
//   tapi.doRawScan(raw, 1, 768, false, true);
//   tapi.awaitScan();
// }

// Repeat for each select line 
 {
   {
     // VREG 0 -> 48
     inter.configure(SCT_SCAN_BOC_V_PHASES, 0, 48, 1);

     // Sample at clock/2 rate
     tapi.doRawScan(inter, 1, 768, false, true);
     tapi.awaitScan();
   }

   // Find a 12ns range which contains the transitions of all the modules
   tapi.modifyBOCParam(SCT_SCAN_BOC_V_PHASES, 24);

   {
     // VERNIER 0 -> 255
     inter.configure(SCT_SCAN_BOC_VRN_FINE, 0, 255, 1);

     // Sample at clock/2 rate
     tapi.doRawScan(inter, 1, 768, false, true);
     tapi.awaitScan();
   }
 }

 // Set up BPM delays and repeat
}

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