/var/pcce/usera/hill/rcc_1.2/RodDaq/RodCrate/TimDefine.h Source File

00001 //File: TimDefine.h
00002 
00003 #ifndef SCTPIXELROD_TIMDEFINE_H
00004 #define SCTPIXELROD_TIMDEFINE_H
00005 
00006 /*! \file
00007  * \brief TimDefine.h: An incomplete prototype definition of a TIM.
00008  *
00009  * NB define eg I_AM_LINUX_HOST for processor.h (eg typedef UINT32)
00010  *
00011  * Contributors: John Lane <jbl@hep.ucl.ac.uk> - originator
00012  *
00013  * $Id: TimDefine.h,v 1.3 2002/12/11 21:30:49 jbl Exp $
00014  *
00015  * $Log: TimDefine.h,v $
00016  * Revision 1.3  2002/12/11 21:30:49  jbl
00017  * TimModule major update
00018  *
00019  *
00020  *
00021  * Reference: http://www.hep.ucl.ac.uk/~jbl/SCT/TIM_registers.html
00022  */
00023 
00024 namespace SctPixelRod {
00025 
00026 #include "../CommonWithDsp/processor.h"
00027 
00028 //! Define timing in clock cycles for SCT, Pixel is different
00029 
00030 enum TimTimingSCT {
00031      TIM_L1A_DEADTIME =  3,
00032      TIM_ECR_DEADTIME =  7,
00033      TIM_BCR_DEADTIME =  7,
00034      TIM_CAL_DEADTIME = 27,
00035      TIM_BCID_OFFSET  =  6
00036 };
00037 
00038 const INT32 TIM_L1ID_FIRST = 0; //!< triggers
00039 
00040 /*! Sequencer RAM is 16K bytes for both source and sink memory.
00041  *  They are accessed together as 16K 16-bit words.
00042  */
00043 const INT32 TIM_SEQ_SIZE = 0x4000; //!< bytes
00044 const INT32 TIM_SEQ_ADDR = 0x8000; //!< bytes
00045 
00046 //! Define register offsets in bytes
00047 
00048 enum TimRegister {
00049      TIM_REG_ENABLES      = 0x00,
00050      TIM_REG_COMMAND      = 0x02,
00051      TIM_REG_BURST_COUNT  = 0x04,
00052      TIM_REG_FREQUENCY    = 0x06,
00053      TIM_REG_WINDOW       = 0x08,
00054      TIM_REG_DELAY        = 0x0A,
00055      TIM_REG_STATUS       = 0x0C,
00056      TIM_REG_FIFO_STATUS  = 0x0E,
00057      TIM_REG_TRIGGER_IDLO = 0x10,
00058      TIM_REG_TRIGGER_IDHI = 0x12,
00059      TIM_REG_TRIGGER_BCID = 0x14,
00060      TIM_REG_TRIGGER_TYPE = 0x16,
00061      TIM_REG_RUN_ENABLES  = 0x18,
00062      TIM_REG_SEQ_CONTROL  = 0x1A,
00063      TIM_REG_SEQ_END      = 0x1C,
00064      TIM_REG_ROD_MASK     = 0x1E,
00065      TIM_REG_ROD_BUSY     = 0x20,
00066      TIM_REG_ROD_LATCH    = 0x22,
00067      TIM_REG_ROD_MONITOR  = 0x24,
00068      TIM_REG_TTC_DATA     = 0x26,
00069      TIM_REG_TTC_SELECT   = 0x28,
00070      TIM_REG_TTC_BCID     = 0x2A,
00071      TIM_REG_TTC_RX       = 0x2C,
00072      TIM_REG_TTC_STATUS   = 0x2E,
00073      TIM_REG_OUTPUT       = 0x30,
00074      TIM_REG_TIM_ID       = 0x32
00075 };
00076 
00077 //! Define register bits as masks
00078 
00079 enum TimBitEnables {
00080      TIM_BIT_EN_INT_TRIG = 0x0002,  //!< Enable internal repetitive Trigger
00081      TIM_BIT_EN_INT_ECR  = 0x0004,  //!< Enable internal repetitive ECReset
00082      TIM_BIT_EN_INT_BCR  = 0x0008,  //!< Enable internal repetitive BCReset
00083      TIM_BIT_EN_RANDOM   = 0x0010,  //!< Enable internal trigger randomizer
00084      TIM_BIT_EN_INT_FER  = 0x0020,  //!< Enable internal repetitive FEReset
00085      TIM_BIT_EN_WINDOW   = 0x0040,  //!< Enable trigger window
00086      TIM_BIT_EN_INT_BUSY = 0x0080,  //!< Enable internal Busy
00087 
00088      TIM_BIT_EN_EXT_CLK  = 0x0100,  //!< Enable external inputs: clock
00089      TIM_BIT_EN_EXT_TRIG = 0x0200,  //!< Enable external inputs: trigger
00090      TIM_BIT_EN_EXT_ECR  = 0x0400,  //!< Enable external inputs: ECReset
00091      TIM_BIT_EN_EXT_BCR  = 0x0800,  //!< Enable external inputs: BCReset
00092      TIM_BIT_EN_EXT_CAL  = 0x1000,  //!< Enable external inputs: Calibrate
00093      TIM_BIT_EN_EXT_FER  = 0x2000,  //!< Enable external inputs: FEReset
00094      TIM_BIT_EN_EXT_SEQ  = 0x4000,  //!< Enable external inputs: Sequencer Go
00095      TIM_BIT_EN_EXT_BUSY = 0x8000   //!< Enable external inputs: Busy
00096 };
00097 
00098 enum TimMaskFrequency {
00099      TIM_MASK_TRIG_100_KHZ = 0x0006,
00100      TIM_MASK_TRIG_10_0KHZ = 0x000E,
00101      TIM_MASK_TRIG_1_00KHZ = 0x0016,
00102      TIM_MASK_TRIG_0_10KHZ = 0x001E,
00103 
00104      TIM_MASK_FER_10_00HZ  = 0x0600,
00105      TIM_MASK_FER_1_000HZ  = 0x0E00,
00106      TIM_MASK_FER_0_100HZ  = 0x1600,
00107      TIM_MASK_FER_0_010HZ  = 0x1E00
00108 };
00109                        //!  Applies to Sequencer and Output
00110 enum TimBitBackplane {
00111      TIM_L1A = 0x01,       //!< Level-1 Accept trigger
00112      TIM_ECR = 0x02,       //!< Event Counter Reset
00113      TIM_BCR = 0x04,       //!< Bunch Counter Reset
00114      TIM_CAL = 0x08,       //!< Calibrate strobe
00115      TIM_SID = 0x10,       //!< Serial event ID
00116      TIM_STT = 0x20,       //!< Serial Trigger Type
00117      TIM_CMD = 0xCF,       //!< Commands available
00118      TIM_RES = 0xC0,       //!< Commands reserved
00119      TIM_FER = 0x40,       //!< Front-End Reset - reserved
00120      TIM_SPA = 0x80,       //!< Spare command   - reserved
00121      TIM_TRG = 0x31        //!< Trigger and serial streams
00122 };
00123                        //!  Applies to Command register
00124 enum TimBitCommand {
00125      TIM_VTRG = 0x02,      //!< Single VME Trigger
00126      TIM_VECR = 0x04,      //!< Single VME ECR
00127      TIM_VBCR = 0x08,      //!< Single VME BCR
00128      TIM_VCAL = 0x10,      //!< Single VME CAL
00129      TIM_VFER = 0x20,      //!< Single VME FER
00130      TIM_VSPA = 0x40,      //!< Single VME SPA
00131 
00132      TIM_BIT_VRESET = 0x8000
00133 };
00134 
00135 enum TimBitRunEnables {
00136      TIM_BIT_EN_ID   = 0x0200,
00137      TIM_BIT_EN_TYPE = 0x0400
00138 };
00139 
00140 enum TimBitSeqControl {
00141      TIM_BIT_SEQ_EN_ALL = 0x00FF,
00142      TIM_BIT_SEQ_RESET  = 0x0200,
00143      TIM_BIT_SEQ_GO     = 0x0400,
00144      TIM_BIT_EN_CYCLIC  = 0x0800
00145 };
00146 
00147 } // End namespace SctPixelRod
00148 
00149 #endif // SCTPIXELROD_TIMDEFINE_H