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/var/pcce/usera/hill/rcc_1.2/RodDaq/RodCrate/BocAddresses.h

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//File: BocAddresses.h

#ifndef SCTPIXELROD_BOCADDRESSES_H
#define SCTPIXELROD_BOCADDRESSES_H

/*!
*  BocAddresses.h is a wrapper around the testBench C code header file
memoryPartitions.h. This wrapper adapts things to appear more like C++ and to
declare things const so the compiler can catch attempts to change them in the
code. Only BOC addresses appear in this file.

Author: J.C.Hill. 8 January 2003. V1.0
*
*/

#include "../CommonWithDsp/processor.h"
#include "../CommonWithDsp/memoryPartitions.h"

namespace SctPixelRod {


// Use only the names in this file in C++ code.

//Get the BOC base address from the testBench definitions.
//CE0_BASE is the start of the window for RRIF registers
//Unfortunately, memoryPartitions.h does not define the BOC
//offset from this base in an available form.

const unsigned long BOC_ADDRESS_BASE =       CE0_BASE + 0x8000;

const unsigned long BOC_ADDRESS_WINDOW =     0x1000;

//The following addresses are offsets from BOC_ADDRESS_BASE for BOC1

//Start with the BPM12 chips - base for channel 0
const unsigned long BOC_BPM_BASE =           0x000;

//Offsets within BPM12 for individual channel functions
enum bocBpmRegisters {
        BOC_BPM_INHIBIT =        0x0,
        BOC_BPM_MARK_SPACE =     0x4,
        BOC_BPM_COARSE =         0x8,
        BOC_BPM_FINE =           0xC
};

//Start addresses for other "blocks" 
const unsigned long BOC_LASER_DAC =          0x600;
const unsigned long BOC_DATA_DELAY =         0x800;
const unsigned long BOC_STROBE_DELAY =       0xA00;
const unsigned long BOC_THRESHOLD_DAC =      0xC00;

//Channel counts (useful for Pixels??)
const unsigned long BOC_TRANSMIT_CHANNELS =  48;
const unsigned long BOC_RECEIVE_CHANNELS =   96;
const unsigned long BOC_STROBE_CHANNELS =    26;

//The following addresses are for single registers.
const unsigned long BOC_BPM_CLK_PHASE =      0x980;
const unsigned long BOC_BREG_CLK_PHASE =     0x98C;
const unsigned long BOC_VERNIER_CLK0_PHASE = 0x990;
const unsigned long BOC_VERNIER_CLK1_PHASE = 0x994;

const unsigned long BOC_RESET =              0xF00;
const unsigned long BOC_BPM_RESET =          0xF04;
const unsigned long BOC_TXDAC_CLEAR =        0xF08;
const unsigned long BOC_RXDAC_CLEAR =        0xF0C;
const unsigned long BOC_STATUS =             0xF10;
const unsigned long BOC_RX_DATA_MODE =       0xF14;
const unsigned long BOC_VERNIER_FINE_PHASE = 0xF20;
const unsigned long BOC_CLK_CONTROL =        0xF28;

const unsigned long BOC_FW_REV =             0xF40;
const unsigned long BOC_HW_REV =             0xF44;
const unsigned long BOC_MODULE_TYPE =        0xF48;
const unsigned long BOC_MANUFACTURER =       0xF4C;
const unsigned long BOC_SERIAL_NUMBER =      0xF60;


//BOC_BUSY_0 is bit 2 of RRIF_STATUS_1. I can't find the definition of
//this register anywhere, so put it here for now.

const unsigned long RRIF_STATUS_1 =          CE0_BASE + 0x4420;
enum rrif_status_1_bits {
        BOC_BUSY_0 =            0x4
};

}; //  End namespace SctPixelRod

#endif //SCTPIXELROD_BOCADDRESSES_H

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