00001 /****************************************************************************** 00002 * 00003 * Title : vmeAddressMap.h 00004 * Version 0.0 00005 * 00006 * Description: Addresses of ROD VME registers. 00007 * Note: All registers except rodStatusRegs are READ/WRITE by Host. 00008 * Related files: ... 00009 * 00010 * Author: Lukas Tomasek, tomasekl@fzu.cz 00011 * 00012 ******************************************************************************/ 00013 00014 #ifndef VME_ADDRESS_MAP_H /* multiple inclusion protection */ 00015 #define VME_ADDRESS_MAP_H 00016 00017 /****************************************************************************** 00018 * Definitions * 00019 ******************************************************************************/ 00020 00021 /* 00022 * VME - HPI interface: 00023 * 00024 * vme_d[15..0] -> hd[15..0] 00025 * vme_a[21] -> hctrl[0] 00026 * vme_a[22] -> hctrl[1] 00027 * vme_a[1] -> hwil 00028 * vme_rnw -> hrnw 00029 * vme_cs_n -> hcs_n 00030 * vme_ds_n -> hds1_n 00031 * vme_dsack0_n <- hrdy_n 00032 * vme_int_n <- hint_n 00033 * vme_be_n[1..0] -> hbe_n[1..0] 00034 */ 00035 00036 00037 #define BASE_ADDRESS(slotNumber) (slotNumber<<24) 00038 00039 /* absoluteVMEaddress = baseAddress + relativeAddress */ 00040 00041 /* 00042 * HPI Registers - 32bit size registers with 2*16bit access!!! 00043 */ 00044 00045 #define HPI_CONTROL_REG_REL_ADDR 0x000000 00046 #define HPI_ADDRESS_REG_REL_ADDR 0x200000 00047 #define HPI_DATA_REG_WITH_AUTOINC_REL_ADDR 0x400000 00048 #define HPI_DATA_REG_WITHOUT_AUTOINC_REL_ADDR 0x600000 00049 00050 /* 00051 * FPGA Program/Reset Manager - 32bit size registers - valid only low 8 bits! 00052 */ 00053 00054 #define FPGA_CONTROL_REG_0_REL_ADDR 0xC00000 /* fpga cnfg control reg */ 00055 #define FPGA_CONTROL_REG_1_REL_ADDR 0xC00004 /* fpga rst control reg */ 00056 #define FPGA_CONTROL_REG_2_REL_ADDR 0xC00008 /* vme dsp rst control reg */ 00057 #define FPGA_CONTROL_REG_3_REL_ADDR 0xC0000C /* flash control reg */ 00058 #define FPGA_CONTROL_REG_4_REL_ADDR 0xC00010 /* flash address(23:0)+data(31:24) reg */ 00059 #define FPGA_CONTROL_REG_5_REL_ADDR 0xC00014 /* */ 00060 #define FPGA_CONTROL_REG_6_REL_ADDR 0xC00018 /* */ 00061 #define FPGA_CONTROL_REG_7_REL_ADDR 0xC0001C /* */ 00062 00063 #define FPGA_STATUS_REG_0_REL_ADDR 0xC00020 /* fpga cnfg status reg */ 00064 #define FPGA_STATUS_REG_1_REL_ADDR 0xC00024 /* fpga reset status reg */ 00065 #define FPGA_STATUS_REG_2_REL_ADDR 0xC00028 /* vme dsp reset status reg */ 00066 #define FPGA_STATUS_REG_3_REL_ADDR 0xC0002C /* fpga init status reg */ 00067 #define FPGA_STATUS_REG_4_REL_ADDR 0xC00030 /* flash status reg */ 00068 #define FPGA_STATUS_REG_5_REL_ADDR 0xC00034 /* halt status */ 00069 #define FPGA_STATUS_REG_6_REL_ADDR 0xC00038 /* ROD serial number */ 00070 #define FPGA_STATUS_REG_7_REL_ADDR 0xC0003C /* flash read data reg */ 00071 00072 00073 /******************************************************************************/ 00074 00075 #endif /* VME_ADDRESS_MAP_H */ 00076
1.3-rc3