memoryPartitions.h Source File

00001 /*************************************************************************************
00002  * memoryPartitions.h
00003  *
00004  *  synopsis: Defines the memory partitions in the DSP memory space.
00005  *            Declares routine for initializing memory.
00006  *            Should be included in the DSP and the VME host code.
00007  *
00008  *   In Project->Options->Compiler it is POSSIBLE to define
00009  *    TI_EVM: EVM DSP has smaller SDRAMs than the ROD DSPs. This option partitions
00010  *            memory accordingly.
00011  *    MAP_0: probably never used, ROD DSPs are wired for MAP_1, see peripherals 
00012  *           manual 10-5
00013  *    SIM:   If defined, handles some aspects of the DSP's environment (for SDSPs,
00014  *           this is the MDSP's responses to their communication register settings;
00015  *           for the MDSP this is the host's & SDSPs' responses. 
00016  *
00017  *  Damon Fasching, UW Madison                            fasching@wisconsin.cern.ch
00018  *  Douglas Ferguson, UW Madison   (510) 486-5230         dpferguson@lbl.gov
00019  *
00020  *  modifications/bugs    
00021  *   - Updated to reflect changes in the project organization. When BIOS was
00022  *     introduced, the program memory sections must be defined inside the config
00023  *     database; the MEMORY section of the linker command file is no longer used &
00024  *     is taken out. External code & data are combined and put the XPROG memory
00025  *     section (FARDATA gone). The default positions and sizes of the 4 text, and
00026  *     the primitive & reply buffers, have changed. 6701s now have 32M of external
00027  *     memory; 6201 still has 16M.                                   26.04.02 dpsf
00028  *
00029  *   - Inter-DSP communication buffers put in SDRAM & communication registers moved
00030  *     to the beginning of internal memory (IDREG segment in the configuration
00031  *     database file) The 2 handshake registers have been left in internal memory
00032  *     with the other registers. A new section of memory, IDATA, has been created
00033  *     for important program variables; they should now remain relatively fixed in
00034  *     one spot instead of floating about in the program IDRAM while code is added
00035  *     & modified, as they did before. This is intended to be used with the
00036  *     DATA_SECTION pragma (see Optimizing C Compiler User's Guide, 7.6.4). Use of
00037  *     the pragma makes variables inaccessible to routines in other files, so
00038  *     use with care. (They can still be accessed by calling a function to return a
00039  *     pointer to them).                                                05.06.02 dpsf
00040  *
00041  *   - Added EXPERT, HCMD, HSTAT, TRAPREQ & TRAPSTAT registers for general purpose
00042  *     use, histogramming, and event trapping respectively. New defined locations in
00043  *     memory were added for the (suggested) base in memory of histograms & the
00044  *     trapping buffer as well.                                         20.06.02 dpsf
00045  *
00046  *   - New memory section MODULE_DATA was added for storage of new module
00047  *     configuration structures on the master.                          03.07.02 dpsf
00048  * 
00049  *  modifications/bugs    
00050  *   - Master & slave DSPs now have different size primitive & reply buffers. The
00051  *     compilation constants HOST_(PRM/REP)_BFR_(BASE/SZ) in memoryPartitions.h have
00052  *     been replaced with different sets for the two DSP types.        10.12.02 dpsf
00053  *************************************************************************************
00054  * NOTE: The segment sizes defined in this file for use in positioning registers and
00055  *       other program items (which are not explicitly declared as variables) must
00056  *   agree with the corresponding memory segment length and base, set in the
00057  *   configuration database file (.cdb). **Otherwise overwrites are possible** The
00058  *   memory order of the segments defined there should be maintained as well. These
00059  *   segment sizes are:
00060  *
00061  *   IDREGS_SZ, IDATA_SZ, IDRAM_MEM_SZ, BURST_SZ, XPROG_SZ, and 
00062  *   (master only) MODULE_DATA_SZ
00063  *
00064  *   IDRAM_SZ is the total size of the DSP IDRAM.
00065  *   (IDRAM_MEM is used here for the memory section IDRAM in the .cdb file, which
00066  *    cannot be renamed.)
00067  ************************************************************************************/
00068 #ifndef MEMORY_PARTITIONS
00069 #define MEMORY_PARTITIONS
00070 
00071 #include "processor.h"
00072 /*
00073  * Each DSP has 0x10000 bytes of internal program memory, IPRAM, starting at 0x0
00074  *              0x10000 bytes of internal data memory, IDRAM, starting at 0x80000000
00075  *              0x1000000 bytes SDRAM starting at 0x2000000 or 0x3000000
00076  *
00077  * Some of this is used for buffers and communication mailboxes whose addresses and
00078  * sizes are defined below.
00079  *
00080  * Memory sections are defined in the configuration database file so that it is
00081  * available for the linker to allocate code, data, stack, heap, etc... The BIOS is
00082  * set up so that it uses an external user linker command file (.cmd) for the
00083  * placement of non-BIOS related memory sections; this file then calls the BIOS .cmd
00084  * file at its finish. 
00085  *
00086  *                      table of available memory spaces
00087  *
00088  * mem space    base address             what's there for each device
00089  *
00090  *               MAP 0      MAP 1        EVM       master DSP      slave DSPs
00091  * EMIF CE0  0x00000000  0x00400000  256KB SBSRAM   RRI FPGA   external registers
00092  * EMIF CE1  0x01000000  0x01400000                 boot ROM         router
00093  * EMIF CE2  0x02000000  0x02000000   4MB SDRAM    16MB SDRAM      16MB SDRAM
00094  * EMIF CE3  0x03000000  0x03000000   4MB SDRAM                    16MB SDRAM
00095  *  IPRAM    0x01400000  0x00000000          64KB internal program memory
00096  *  IDRAM    0x80000000  0x80000000          64KB intermal data memory   
00097  *
00098  *************************************************************************************
00099  *                   sizes of the available memories.
00100  ************************************************************************************/
00101 #define IPRAM_SZ       (0x10000)   /* 64KB of internal program memory */
00102 #define IDRAM_SZ       (0x10000)   /* 64KB of internal data memory */
00103 #if (defined(I_AM_SLAVE_DSP)&&defined(REV_E))
00104     #define SRAM_SZ_NO_CACHE        (0x40000)
00105     #define SRAM_SZ_16K_CACHE       (0x3c000)
00106     #define SRAM_SZ_32K_CACHE       (0x38000)
00107     #define SRAM_SZ_48K_CACHE       (0x34000)
00108     #define SRAM_SZ_64K_CACHE       (0x30000)
00109 #endif
00110 
00111 #ifdef TI_EVM
00112     #define SDRAM0_SZ  (0x400000)  /* 4MB of SDRAM available at CE2 on the EVM */
00113     #define SDRAM1_SZ  (0x400000)  /* 4MB of SDRAM available at CE3 on the EVM */
00114 
00115 #else                             
00116     #if (defined(I_AM_MASTER_DSP) || defined(I_AM_NT_HOST) || defined(I_AM_LINUX_HOST))
00117         #define SDRAM0_SZ  (0x800000)  /*  16 MB of SDRAM available on the ROD */
00118         #define SDRAM1_SZ  (0x800000)  /*  divided into two halves both on CE2 */
00119     #elif (defined(I_AM_SLAVE_DSP))
00120         #if (defined(REV_B)||defined(REV_C))
00121             #define SDRAM0_SZ  (0x01000000)
00122             #define SDRAM1_SZ  (0x01000000)
00123         #elif defined(REV_E)
00124             #define SDRAM0_SZ  (0x08000000)
00125             #define SDRAM1_SZ  (0x08000000)
00126         #endif
00127     #endif
00128 #endif
00129 
00130 /************************************************************************************
00131  *                  base addresses the available memories
00132  ************************************************************************************/
00133 /* internal program, internal data and 4 EMIF chip enables for off chip memories */
00134 #if (   (defined(I_AM_MASTER_DSP)) || (defined(I_AM_NT_HOST)) || (defined(I_AM_LINUX_HOST)) \
00135      || (defined(I_AM_SLAVE_DSP)&&(defined(REV_B)||defined(REV_C)))  )
00136     #ifdef MAP_0
00137         #define CE0_BASE   (0x00000000)
00138         #define CE1_BASE   (0x01000000)
00139         #define IPRAM_BASE (0x01400000)
00140     #else
00141         #define CE0_BASE   (0x00400000)
00142         #define CE1_BASE   (0x01400000)
00143         #define IPRAM_BASE (0x00000000)
00144     #endif
00145     
00146     #define CE2_BASE   (0x02000000)
00147     #define CE3_BASE   (0x03000000)
00148     #define IDRAM_BASE (0x80000000)
00149 
00150 #elif (defined(I_AM_SLAVE_DSP)&&defined(REV_E))
00151     #define CE0_BASE   (0x80000000)
00152     #define CE1_BASE   (0x90000000)
00153     #define SRAM_BASE  (0x00000000)
00154     #define IPRAM_BASE (0x00000000)
00155     
00156     #define CE2_BASE   (0xa0000000)
00157     #define CE3_BASE   (0xb0000000)
00158     #define IDRAM_BASE (0x00010000)
00159 #endif
00160 
00161 
00162 /* SDRAM: EVM has 2 4MB SDRAMs at CE2 and CE3; ROD has 16 MB SDRAM at CE2
00163    + another 16M at CE3 for 6701s */
00164 #define SDRAM0_BASE  (CE2_BASE)
00165 #ifdef TI_EVM
00166     #define SDRAM1_BASE  (CE3_BASE)
00167 #else
00168     #if (defined(I_AM_MASTER_DSP)|| defined(I_AM_NT_HOST) || defined(I_AM_LINUX_HOST))
00169         #define SDRAM1_BASE  (CE2_BASE) + (SDRAM0_SZ)
00170     #elif (defined(I_AM_SLAVE_DSP))
00171         #define SDRAM1_BASE  (CE3_BASE)
00172     #endif
00173 #endif
00174 
00175 /* The master DSP has a boot ROM at CE1; slaves each have a router FIFO */
00176 #ifndef TI_EVM
00177     #if (defined(I_AM_MASTER_DSP) || defined(I_AM_NT_HOST) || defined(I_AM_LINUX_HOST))
00178         #define BOOT_ROM_BASE   (CE1_BASE)
00179         #define BOOT_ROM_SZ     (0x80000)      /* boot ROM is 512K */
00180     #elif (defined(I_AM_SLAVE_DSP))
00181         #define ROUTER_FIFO_BASE   (CE1_BASE)
00182         #define ROUTER_FIFO_SZ     (0x1000)      /* 1K words */
00183     #endif
00184 #endif
00185 
00186 
00187 /************************************************************************************
00188  *                                IDRAM items
00189  ************************************************************************************
00190  * IDREGS_SZ bytes of IDRAM are reserved for communications registers.
00191  * IDATA_SZ  bytes are reserved for important variables for which it's desirable they
00192  *           be kept (for monitoring) in a fixed location. Note that this method has a
00193  *   minor drawback in that the variables become 'far' data objects, they cannot be
00194  *   declared 'external' and thus cannot be directly accessed by functions from files
00195  *   other than the one that they were declared in; they must be accessed through
00196  *   function calls to functions residing in the same file. See accessRegister.c and
00197  *   eventHandler.c for examples. 
00198  * IDRAM_MEM_SZ bytes are reserved for the linker to place general heap, stack and 
00199  *              'near' data objects (arrays and structures which are not declared
00200  *   'far'). This memory corresponds to the IDRAM memory segment in the .cdb file. In
00201  *   the slaves it also holds initialization data for variable values and constants.
00202  *
00203  * BURST_SZ bytes of IDRAM are reserved for the program to store data for immediate
00204  *          use. On the slaves it might be a temporary store for data retrieved from
00205  *   the router FPGA via DMA.  This data might be quickly checked for errors and dumped
00206  *   if none are found or analysed if errors are found.  Or the data might be processed
00207  *   and added to histograms being accumulated in the SDRAM.  On the master it might be
00208  *   a temporary store for data being transmitted to the front end electronics.
00209  *
00210  * **** THESE SIZES MUST BE THE SAME AS THE CORRESPONDING LENGTH PARAMETER OF MEMORY
00211  *      SECTION MANAGER IN THE CONFIGURATION DATABASE FILE ****
00212  *
00213  * NOTE: If the memory section sizes are mistaken, the error will sometimes be caught
00214  *       by the compiler at compile time. Another check is done at run time inside
00215  *   checkMemBounds.c. Most larger data objects like the primitive buffers, text
00216  *   buffers, and external burst buffers do not have variables and memory segments
00217  *   declared for them; for these the space is 'virtually' allocated here and checked
00218  *   in chekMemBounds.c
00219  *
00220  */
00221 #define IDREGS_SZ      (0x0060)
00222 #define IDATA_SZ       (0x0800)
00223 #define IDRAM_MEM_SZ   (0x77a0)
00224 #define BURST_SZ       (0x8000) 
00225 
00226 #define IDRAM_ALLOCATED ((IDREGS_SZ)+(IDATA_SZ)+(IDRAM_MEM_SZ)+(BURST_SZ))
00227 
00228 #define IDREGS_BASE     (IDRAM_BASE)
00229 #define IDATA_BASE      ((IDREGS_BASE) + (IDREGS_SZ))
00230 #define IDRAM_MEM_BASE  ((IDATA_BASE)  + (IDATA_SZ))  /* IDRAM_BASE is kept for the
00231                                                          physical memory base   */
00232 #define BURST_BFR_BASE   ((IDRAM_MEM_BASE) + (IDRAM_MEM_SZ))
00233 
00234 /* communication registers: used for the handshake for host to DSP primitive lists */
00235 /* 0x00 */
00236 #define STATUS_REG_0     (IDRAM_BASE)
00237 #define STATUS_REG_1     ((STATUS_REG_0)   + sizeof(UINT32))
00238 #define STATUS_REG_2     ((STATUS_REG_1)   + sizeof(UINT32))
00239 #define COMMAND_REG_0    ((STATUS_REG_2)   + sizeof(UINT32))
00240 
00241 /* 0x10 */
00242 #define DIAGNOSTIC_REG   ((COMMAND_REG_0)  + sizeof(UINT32))
00243 #define TRAPSTAT_REG_0   ((DIAGNOSTIC_REG) + sizeof(UINT32))
00244 #define TRAPSTAT_REG_1   ((TRAPSTAT_REG_0) + sizeof(UINT32))
00245 #define LOOP_REG         ((TRAPSTAT_REG_1) + sizeof(UINT32))
00246 
00247 /* 0x20 */
00248 #define HCMD_STAT_REG_0  ((LOOP_REG)        + sizeof(UINT32))
00249 #define HCMD_STAT_REG_1  ((HCMD_STAT_REG_0) + sizeof(UINT32))
00250 #define HSTAT_REG_0      ((HCMD_STAT_REG_1) + sizeof(UINT32))
00251 #define HSTAT_REG_1      ((HSTAT_REG_0)     + sizeof(UINT32))
00252 
00253 /* 0x30 */
00254 #define RESERVED_REG_0   ((HSTAT_REG_1)    + sizeof(UINT32))
00255 #define RESERVED_REG_1   ((RESERVED_REG_0) + sizeof(UINT32))
00256 #define RESERVED_REG_2   ((RESERVED_REG_1) + sizeof(UINT32))
00257 #define RESERVED_REG_3   ((RESERVED_REG_2) + sizeof(UINT32))
00258 
00259 /* 0x40 */
00260 #define RESERVED_REG_4   ((RESERVED_REG_3) + sizeof(UINT32))
00261 #define RESERVED_REG_5   ((RESERVED_REG_4) + sizeof(UINT32))
00262 #define MEMORY_MAP_REG   ((RESERVED_REG_5) + sizeof(UINT32))
00263 #define TASK_STATE_REG   ((MEMORY_MAP_REG) + sizeof(UINT32))
00264 
00265 /* 0x50 */
00266 #define HCMD_REG         ((TASK_STATE_REG) + sizeof(UINT32))
00267 #define TRAP_CMD_STAT    ((HCMD_REG)       + sizeof(UINT32))
00268   
00269 /* inter-dsp communication registers: used for the handshake between master and
00270  * slave DSPs when one sends a list for the other to process.  These registers
00271  * reside in the IDRAM of each slave DSP.  The addresses are known to both the
00272  * master and the slaves.  Note that the write register for the slave is the read
00273  * register for the master and vice versa. 
00274  *
00275  * These are NOT used in COMPACT mode, but they are still defined for the
00276  * alignment of the text, primitive and reply buffers. */
00277 #if (defined(I_AM_MASTER_DSP) || defined(I_AM_NT_HOST) || defined(I_AM_LINUX_HOST))
00278     #define INTR_DSP_HSHK_WR  ((TRAP_CMD_STAT)    + sizeof(UINT32))
00279     #define INTR_DSP_HSHK_RD  ((INTR_DSP_HSHK_WR) + sizeof(UINT32))
00280 #elif defined(I_AM_SLAVE_DSP)
00281     #define INTR_DSP_HSHK_RD  ((TRAP_CMD_STAT)    + sizeof(UINT32))
00282     #define INTR_DSP_HSHK_WR  ((INTR_DSP_HSHK_RD) + sizeof(UINT32))
00283 #endif
00284 
00285 /************************************************************************************
00286  *                                SDRAM0 items
00287  ************************************************************************************
00288  *** THIS MUST BE THE SAME AS THE LENGTH PARAMETER OF MEMORY SECTION XPROG IN
00289  *   THE LINKER COMMAND FILE *****/
00290 #define XPROG_SZ   (0x40000)
00291   /* The ERR, INFO, DIAG and XFER buffers are the text buffers for sending messages
00292    * upstream to the host processor.  Slave text buffers are communicated to the host
00293    * via the master XFER buffer.  The XFER buffer is not used on the slaves.
00294    * The HOST_PRM and HOST_REP buffers are for primitive lists from the host and the
00295    * associated reply data.  Host to slave primitive and associated reply data are
00296    * transferred via the master DSP. The inter-DSP transfer buffers are small buffers
00297    * used for sending simple primitive lists from DSP to DSP (master to slave and
00298    * vice-versa). Note that in COMPACT mode the buffers are actually in IDRAM. */
00299 
00300 #ifdef COMPACT
00301   #define TXT_BFR_SZ       (0x800)
00302   #define INTR_DSP_PRM_BFR_SZ  (0x800)
00303   #define INTR_DSP_REP_BFR_SZ  (0x800)
00304 
00305   #if (defined(I_AM_MASTER_DSP) || defined(I_AM_NT_HOST) || defined(I_AM_LINUX_HOST))
00306     #define MDSP_PRM_BFR_SZ  (0x2000)
00307     #define MDSP_REP_BFR_SZ  (0x2000)
00308   #endif
00309   #define SDSP_PRM_BFR_SZ  (0x2000)
00310   #define SDSP_REP_BFR_SZ  (0x2000)
00311 
00312   #define ERR_BFR_BASE       (BURST_BFR_BASE)
00313   #define INFO_BFR_BASE      ((ERR_BFR_BASE)  + (TXT_BFR_SZ))
00314   #define DIAG_BFR_BASE      ((INFO_BFR_BASE) + (TXT_BFR_SZ))
00315   #define XFER_BFR_BASE      ((DIAG_BFR_BASE) + (TXT_BFR_SZ))
00316 
00317   #define INTR_DSP_PRM_BFR_BASE_SND ((XFER_BFR_BASE) +(TXT_BFR_SZ))
00318   #define INTR_DSP_REP_BFR_BASE_SND ((INTR_DSP_PRM_BFR_BASE_SND)+(INTR_DSP_PRM_BFR_SZ))
00319   #define INTR_DSP_PRM_BFR_BASE_PRC ((INTR_DSP_REP_BFR_BASE_SND)+(INTR_DSP_REP_BFR_SZ))
00320   #define INTR_DSP_REP_BFR_BASE_PRC ((INTR_DSP_PRM_BFR_BASE_PRC)+(INTR_DSP_PRM_BFR_SZ))
00321 
00322   #if (defined(I_AM_MASTER_DSP) || defined(I_AM_NT_HOST) || defined(I_AM_LINUX_HOST))
00323     #define MDSP_PRM_BFR_BASE  ((INTR_DSP_REP_BFR_BASE_PRC) + (INTR_DSP_PRM_BFR_SZ))
00324     #define MDSP_REP_BFR_BASE  ((MDSP_PRM_BFR_BASE) + (MDSP_PRM_BFR_SZ)) 
00325   #endif
00326   #define SDSP_PRM_BFR_BASE  ((INTR_DSP_REP_BFR_BASE_PRC) + (INTR_DSP_PRM_BFR_SZ))
00327   #define SDSP_REP_BFR_BASE  ((SDSP_PRM_BFR_BASE) + (SDSP_PRM_BFR_SZ)) 
00328 
00329   #define XBURST_BFR_BASE  ((SDRAM0_BASE) + (XPROG_SZ))
00330   #define XBURST_BFR_SZ    (0x38000) 
00331 
00332   #define BURST_BFR_RESERVED_BASE ((XBURST_BFR_BASE) +(XBURST_BFR_SZ))
00333   #define BURST_BFR_RESERVED_SZ   (0x8000)
00334 
00335   #define HISTOGRAM_DEFAULT_BASE   ((BURST_BFR_RESERVED_BASE) +(BURST_BFR_RESERVED_SZ))
00336   #define SDRAM0_ALLOCATED ((HISTOGRAM_DEFAULT_BASE) -(SDRAM0_BASE))
00337 
00338 #else
00339 
00340   #define TXT_BFR_SZ       (0x8000)
00341   #define INTR_DSP_PRM_BFR_SZ  (0x800)
00342   #define INTR_DSP_REP_BFR_SZ  (0x800)
00343 
00344   /* WARNING: In non-COMPACT compilations, the master & slave DSPs now have
00345               different size primitive & reply buffers. To accomodate this those
00346        buffers have different compilation constants defined. it also means that THE
00347        DSP_(PRM/REP)_BFR_BASE DEFINITIONS MUST BE THE LAST DEFINITIONS WHICH ARE
00348        COMMON TO BOTH DSP TYPES. THE TEXT BUFFERS AND INTER-DSP PRIM BUFFERS MUST
00349        BE DEFINED BEFORE THEM. */
00350   #if (defined(I_AM_MASTER_DSP) || defined(I_AM_NT_HOST) || defined(I_AM_LINUX_HOST))
00351     #define MDSP_PRM_BFR_SZ  (0x50000)
00352     #define MDSP_REP_BFR_SZ  (0x50000)
00353   #endif
00354   #define SDSP_PRM_BFR_SZ  (0x20000)
00355   #define SDSP_REP_BFR_SZ  (0x20000)
00356 
00357 #if (   (defined(I_AM_MASTER_DSP)) || (defined(I_AM_NT_HOST)) || (defined(I_AM_LINUX_HOST)) \
00358      || (defined(I_AM_SLAVE_DSP)&&(defined(REV_B)||defined(REV_C)))  )
00359   #define ERR_BFR_BASE       ((SDRAM0_BASE) + (XPROG_SZ))
00360   #define INFO_BFR_BASE      ((ERR_BFR_BASE)  + (TXT_BFR_SZ))
00361   #define DIAG_BFR_BASE      ((INFO_BFR_BASE) + (TXT_BFR_SZ))
00362   #define XFER_BFR_BASE      ((DIAG_BFR_BASE) + (TXT_BFR_SZ))
00363 
00364 #elif (defined(I_AM_SLAVE_DSP)&&defined(REV_E))
00365   #define ERR_BFR_BASE1       0x20000
00366   #define INFO_BFR_BASE1      0x28000
00367 
00368   #define ERR_BFR_BASE       ((SDRAM0_BASE) + (XPROG_SZ))
00369   #define INFO_BFR_BASE      ((ERR_BFR_BASE)  + (TXT_BFR_SZ))
00370   #define DIAG_BFR_BASE      ((INFO_BFR_BASE) + (TXT_BFR_SZ))
00371   #define XFER_BFR_BASE      ((DIAG_BFR_BASE) + (TXT_BFR_SZ))
00372 #endif
00373 
00374 
00375   #define INTR_DSP_PRM_BFR_BASE_SND ((XFER_BFR_BASE) +(TXT_BFR_SZ))
00376   #define INTR_DSP_REP_BFR_BASE_SND ((INTR_DSP_PRM_BFR_BASE_SND)+(INTR_DSP_PRM_BFR_SZ))
00377   #define INTR_DSP_PRM_BFR_BASE_PRC ((INTR_DSP_REP_BFR_BASE_SND)+(INTR_DSP_REP_BFR_SZ))
00378   #define INTR_DSP_REP_BFR_BASE_PRC ((INTR_DSP_PRM_BFR_BASE_PRC)+(INTR_DSP_PRM_BFR_SZ))
00379 
00380   #if (defined(I_AM_MASTER_DSP) || defined(I_AM_NT_HOST) || defined(I_AM_LINUX_HOST))
00381     #define MDSP_PRM_BFR_BASE  ((INTR_DSP_REP_BFR_BASE_PRC) + (INTR_DSP_PRM_BFR_SZ))
00382     #define MDSP_REP_BFR_BASE  ((MDSP_PRM_BFR_BASE) + (MDSP_PRM_BFR_SZ)) 
00383     #define CMD_BUFFER_BASE    ((MDSP_REP_BFR_BASE) + (MDSP_REP_BFR_SZ))
00384     #define CMD_BUFFER_SZ      0x8000
00385     #define SDRAM0_FREE_BASE   ((CMD_BUFFER_BASE) +(CMD_BUFFER_SZ))
00386 
00387   #endif
00388   #define SDSP_PRM_BFR_BASE  ((INTR_DSP_REP_BFR_BASE_PRC) + (INTR_DSP_PRM_BFR_SZ))
00389   #define SDSP_REP_BFR_BASE  ((SDSP_PRM_BFR_BASE) + (SDSP_PRM_BFR_SZ)) 
00390 
00391   #if (defined(I_AM_SLAVE_DSP) || defined(I_AM_NT_HOST) || defined(I_AM_LINUX_HOST))
00392     #define XBURST_BFR_BASE           ((SDSP_REP_BFR_BASE)+(SDSP_REP_BFR_SZ))
00393     #define XBURST_BFR_SZ             (0x38000) 
00394     
00395     #define BURST_BFR_RESERVED_BASE ((XBURST_BFR_BASE) +(XBURST_BFR_SZ))
00396     #define BURST_BFR_RESERVED_SZ   (0x8000)
00397     
00398     #define HISTOGRAM_DEFAULT_BASE  ((BURST_BFR_RESERVED_BASE) +(BURST_BFR_RESERVED_SZ))
00399 
00400   #endif
00401 
00402   #if   defined(I_AM_MASTER_DSP)
00403     #define SDRAM0_ALLOCATED ((SDRAM0_FREE_BASE) -(SDRAM0_BASE))
00404   #elif defined(I_AM_SLAVE_DSP)
00405     #define SDRAM0_ALLOCATED ((HISTOGRAM_DEFAULT_BASE) -(SDRAM0_BASE))
00406   #endif
00407 
00408   #define MODULE_DATA_BASE    0x02400000
00409   #if   defined(SCT_ROD)
00410     #define MODULE_DATA_SZ      0x00080000      /* .5 MB */
00411   #elif defined(PIXEL_ROD)
00412     #define MODULE_DATA_SZ      0x00b00000      /* 11 MB */
00413   #endif
00414 
00415 #endif
00416 
00417 /* default position for trapped events is in high memory: whereas the burst buffers
00418    are always needed for trapping events, this is potentially reserved memory for
00419    gathering trapped events; it is intended to be a suggestion when running the event
00420    trapping task. */
00421 #if  (defined(I_AM_MASTER_DSP) || defined(I_AM_NT_HOST) || defined(I_AM_LINUX_HOST))
00422     #define SLV_SDRAM1_BASE          (0x03000000)
00423     #define SLV_SDRAM1_SZ            (0x01000000)   /* needed by VME host */
00424     #define EVENT_TRAP_DEFAULT_SZ    (0x20000)
00425     #define EVENT_TRAP_DEFAULT_BASE  ((SLV_SDRAM1_BASE) +(SLV_SDRAM1_SZ) \
00426                                       -(EVENT_TRAP_DEFAULT_SZ))
00427 #else
00428     #define EVENT_TRAP_DEFAULT_SZ    (0x20000)
00429     #define EVENT_TRAP_DEFAULT_BASE  ((SDRAM1_BASE) +(SDRAM1_SZ) \
00430                                       -(EVENT_TRAP_DEFAULT_SZ))
00431 #endif
00432 
00433 /* SDRAM1: Free space for application defined data on SCT RODs; for Pixel RODs
00434            the module database takes up the last 4 MB of SDRAM0 & the first 7
00435            MB of SDRAM1 (see above) & the upper 1 MB is free space. */
00436 #if (defined(I_AM_MASTER_DSP) || defined(I_AM_NT_HOST) || defined(I_AM_LINUX_HOST))
00437 
00438     #define MEMORY_LIMIT  0x03000000
00439     /* if running on the TI evaluation module, the 6701 DSP communication registers
00440        must be offset, and the RRIF must be faked. A small amount of slave memory is
00441        faked as well. These are put right before the end of memory. */
00442     #define EVM_SLV_REG_BASE(slv)    (MEMORY_LIMIT - 0x18200 + 0x80*(slv))
00443     #define EVM_SLV_MEM_BASE(slv)    (MEMORY_LIMIT - 0x18000 + 0x2000*(slv))
00444     #define EVM_RRIF_REG_BASE        ((MEMORY_LIMIT) - 0x10000)
00445 
00446     #define SDRAM1_FREE_BASE   (SDRAM1_BASE)
00447 #else 
00448     #define SDRAM1_FREE_BASE   (SDRAM1_BASE)
00449 #endif
00450 
00451 #define SDRAM1_ALLOCATED   0
00452 
00453 #if defined(TI_EVM)  /* need a histogram base for SDRAM1 */
00454     #define HISTOGRAM_BASE1   ((SDRAM1_BASE) +(0x40000))
00455 #endif
00456 
00457 /************************************************************************************
00458  *    RRIF memory mapped items - CE0 on ROD; EVM_RRIF_REG_BASE on TI_EVM/SIM (no RRIF)
00459  ************************************************************************************/
00460 #if defined(I_AM_MASTER_DSP) 
00461     /* base address for memory mapped registers and FIFOs */
00462 
00463     #if (defined(TI_EVM) || defined(SIM))
00464         #define REG_BASE (EVM_RRIF_REG_BASE)
00465     #else
00466         #define REG_BASE    (CE0_BASE)
00467     #endif
00468     
00469     /* offsets into each device  These are RRIF-centric offsets, i.e. from the DSP
00470      * point of view they need to be left shifted 2 bits.  This is done where needed
00471      * in the files containing the access routines. */
00472     #define FMT_BASE  (0x0)
00473     #define EFB_BASE  (0x800)
00474     #define RTR_BASE  (0x900)
00475     #define RRIF_BASE (0x1000)
00476     #define FIFO_BASE (0x1800)
00477     #define BOC_BASE  (0x2000)
00478     #define SLV_BASE  (0xE0000)
00479     
00480     #define LED_OFFSET 0x100
00481     #define HEARTBEAT_ADR ((UINT32 *)(((RRIF_BASE + LED_OFFSET) << 2) + REG_BASE))
00482     
00483 #elif defined(I_AM_SLAVE_DSP)
00484     #define ROUTER_FIFO_ADDR       (CE1_BASE)
00485 
00486 #endif
00487 
00488 #endif