Precision RTL Synthesis 2011a_Update2.76 (Production Release) Tue Nov 8 06:37:47 PST 2011
Copyright (c) Mentor Graphics Corporation, 1996-2011, All Rights Reserved. Start time Thu Aug 02 10:13:11 2012 |
| Processor(s): | 1 Processor(s) Installed. |
| [01]: Intel64 Family 6 Model 23 Stepping 10 GenuineIntel ~3000 Mhz |
| Total Physical Memory: | 4,052 MB |
| Available Physical Memory: | 2,102 MB |
| Virtual Memory: Max Size: | 8,103 MB |
| Virtual Memory: Avaliable: | 6,270 MB |
| Virtual Memory: In Use: | 1,833 MB |
| OS Name: | Windows 7 |
| OS Version: | 6.1.7601 Service Pack 1 Build 7601 |
| Hotfix(s): | 85 Hotfix(s) Installed. |
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## Technology Settings
setup_design -manufacturer Xilinx -family SPARTAN2E -part 2s50etq144 -speed 6
## Input File Settings
setup_design -design="Cosmixer"
setup_design -arch="struct"
set_input_dir Z:/HDL/Cosmix/Cosmix_lib/hdl
add_input_file -format VHDL -work Cosmix_lib {Cosmix_pkg.vhd}
add_input_file -format VHDL -work Cosmix_lib {z:/HDL/Cosmix/Cosmix_lib/hdl/Flash_Simple.vhd}
add_input_file -format VHDL -work Cosmix_lib {z:/HDL/Cosmix/Cosmix_lib/hdl/sphitblock_struct.vhd}
add_input_file -format VHDL -work Cosmix_lib {z:/HDL/Cosmix/Cosmix_lib/hdl/@inv.vhd}
add_input_file -format VHDL -work Cosmix_lib {z:/HDL/Cosmix/Cosmix_lib/hdl/SpCoLog_Simple.vhd}
add_input_file -format VHDL -work Cosmix_lib {z:/HDL/Cosmix/Cosmix_lib/hdl/spcoblock_struct.vhd}
add_input_file -format VHDL -work Cosmix_lib {z:/HDL/Cosmix/Cosmix_lib/hdl/obufn_struct.vhd}
add_input_file -format VHDL -work Cosmix_lib {z:/HDL/Cosmix/Cosmix_lib/hdl/SPI_CTR_Mk2.vhd}
add_input_file -format VHDL -work Cosmix_lib {z:/HDL/Cosmix/Cosmix_lib/hdl/SPI_DAC_Mk3.vhd}
add_input_file -format VHDL -work Cosmix_lib {z:/HDL/Cosmix/Cosmix_lib/hdl/ClockGen_SIMPLE.vhd}
add_input_file -format VHDL -work Cosmix_lib {z:/HDL/Cosmix/Cosmix_lib/hdl/gckgen_struct.vhd}
add_input_file -format TCL -work work {Z:/HDL/Cosmix/Cosmix_lib/ps/TopSpark_struct/hds/add_files.tcl}
add_input_file -format VHDL -work Cosmix_lib {count_struct.vhd}
add_input_file -format VHDL -work Cosmix_lib {hit_stretch.vhd}
add_input_file -format VHDL -work Cosmix_lib {spi_cfg.vhd}
add_input_file -format VHDL -work Cosmix_lib {delay_struct.vhd}
add_input_file -format VHDL -work Cosmix_lib {cosmixer_struct.vhd}
## Output File Settings
setup_design -basename="cosmixer"
## Design Settings
setup_design -addio
setup_design -addio_unused=false
setup_design -vhdl=false
setup_design -verilog=false
setup_design -edif
setup_design -vqm=false
setup_design -vendor_constraint_file
setup_design -transformations
setup_design -retiming
setup_design -altera_dsp_retiming=false
setup_design -pa_io_pin_location=false
setup_design -advanced_fsm_optimization
setup_design -compile_for_area=false
setup_design -compile_for_timing
setup_design -safe_fsm_type="basic"
setup_design -encoding="onehot"
setup_design -resource_sharing
setup_design -array_bounds_check=false
setup_design -transform_tristates="auto"
setup_design -process_tristates=false
setup_design -edif_bus_extraction_style="%s(%d:%d)"
setup_design -black_box_flow=false
setup_design -bottom_up_flow=false
setup_design -white_box_flow
setup_design -retain_inouts
setup_design -frequency="50"
setup_design -radhardmethod="none"
setup_design -tmr_dc_portname=""
setup_design -tmr_dc_logic="none"
setup_design -tmr_use_shiftregs
setup_design -tmr_use_distram=false
setup_design -tmr_vote_only_fault_retention_paths=false
setup_design -tmr_remove_halflatch=false
setup_design -tmr_input="converged"
setup_design -tmr_output="converged"
setup_design -tmr_block=false
setup_design -input_delay="5"
setup_design -output_delay="5"
setup_design -boundary_opt
setup_design -partition_size="80000"
setup_design -global_clock_limit=""
setup_design -infer_gsr
setup_design -infer_muxed_arith_operators
setup_design -clearbox=false
setup_design -search_path {}
setup_design -libext=""
setup_design -y {}
setup_design -mem_init_path {}
setup_design -altera_mangle_prefix="_MGC"
setup_design -2004c_compile_mode=false
setup_design -enable_synthoff_regions=false
setup_design -overrides {}
setup_design -hdl { verilog systemverilog vhdl_2002 }
setup_design -defines {}
setup_design -automap_work=false
setup_design -error_design_contention=false
setup_design -all_file_cunit_scope=false
setup_design -sv31acompat=false
setup_design -vcs_compat=false
setup_design -compile_udps=false
setup_design -relaxed_compile=false
setup_design -vendor_override_lib="xilinx"
setup_design -max_loop_count=5000
setup_design -ignore_ram_rw_collision=false
setup_design -altera_netlist_opt=false
set_path_compression_options -run_during_physical_synthesis=false
setup_design -sta_time_resolution=-12
setup_design -gated_clock=1
setup_design -auto_save_placement
setup_design -auto_resource_allocation_ram=false
setup_design -enable_incr_synth=false
setup_design -enable_incr_pnr=false
setup_design -dsp_across_hier=false
setup_design -extensive_dsp_drc
setup_design -relax_dsp_drc=false
setup_design -flatten_small_rtl_modules=false
setup_design -timequest_sdc=false
setup_design -reencode_fsm_outputs
setup_design -dont_pass_synthesis_define=false
setup_design -max_fanout=10000
setup_design -max_fanout_strategy="AUTO"
setup_design -compile_initial_values=false
setup_design -block_ram_cutoff=0
setup_design -block_rom_cutoff=0
setup_design -infer_ram
setup_design -infer_rom
setup_design -control_set_optimize
setup_design -control_set_threshold=6
setup_design -modgen="auto"
setup_design -modgen_mode="auto"
setup_design -lut_combine="off"
setup_design -fv_flow="none"
setup_design -gate_level_opt=false
setup_design -assured_synthesis=false
setup_design -flatten_small_blocks=false
setup_design -write_verilog_escape_names=false
setup_design -compatibility_mode="none"
setup_design -preserve_instantiated_cells=false
setup_design -ignore_utilization=false
## Place and Route Settings for Flow 'ISE 5.1' Command 'Integrated Place and Route'
setup_place_and_route -flow "ISE 5.1" -command "Integrated Place and Route" -install_dir {$XILINX}
setup_place_and_route -flow "ISE 5.1" -command "Integrated Place and Route" -no_exec {0}
setup_place_and_route -flow "ISE 5.1" -command "Integrated Place and Route" -smartguide {0}
setup_place_and_route -flow "ISE 5.1" -command "Integrated Place and Route" -smartguide_file {"*.ncd \"\""}
setup_place_and_route -flow "ISE 5.1" -command "Integrated Place and Route" -optimization_control {std}
setup_place_and_route -flow "ISE 5.1" -command "Integrated Place and Route" -global_opt {off}
setup_place_and_route -flow "ISE 5.1" -command "Integrated Place and Route" -disable_logic_replication {0}
setup_place_and_route -flow "ISE 5.1" -command "Integrated Place and Route" -do_not_remove_unused_logic {0}
setup_place_and_route -flow "ISE 5.1" -command "Integrated Place and Route" -ignore_keep_hierarchy {0}
setup_place_and_route -flow "ISE 5.1" -command "Integrated Place and Route" -par_ol {high}
setup_place_and_route -flow "ISE 5.1" -command "Integrated Place and Route" -ba_format {VHDL}
setup_place_and_route -flow "ISE 5.1" -command "Integrated Place and Route" -timing_paths_per_constraint {10}
setup_place_and_route -flow "ISE 5.1" -command "Integrated Place and Route" -bits {0}
## Place and Route Settings for Flow 'ISE 5.1' Command 'Generate Vendor Constraint File'
setup_place_and_route -flow "ISE 5.1" -command "Generate Vendor Constraint File" -enable_auto_offset_relaxation {0}
setup_place_and_route -flow "ISE 5.1" -command "Generate Vendor Constraint File" -use_ucf_timing_constraints {False}
setup_place_and_route -flow "ISE 5.1" -command "Generate Vendor Constraint File" -no_exec {0}
## Place and Route Settings for Flow 'ISE 5.1' Command 'Advanced Options'
setup_place_and_route -flow "ISE 5.1" -command "Advanced Options" -use_pnr_script_cl {0}
setup_place_and_route -flow "ISE 5.1" -command "Advanced Options" -pnr_script_cl {user_pnr_script.tcl}
## Place and Route Settings for Flow 'ISE' Command 'Integrated Place and Route'
setup_place_and_route -flow ISE -command "Integrated Place and Route" -install_dir {$XILINX}
setup_place_and_route -flow ISE -command "Integrated Place and Route" -no_exec {0}
setup_place_and_route -flow ISE -command "Integrated Place and Route" -smartguide {0}
setup_place_and_route -flow ISE -command "Integrated Place and Route" -smartguide_file {"*.ncd \"\""}
setup_place_and_route -flow ISE -command "Integrated Place and Route" -optimization_control {std}
setup_place_and_route -flow ISE -command "Integrated Place and Route" -global_opt {off}
setup_place_and_route -flow ISE -command "Integrated Place and Route" -disable_logic_replication {0}
setup_place_and_route -flow ISE -command "Integrated Place and Route" -do_not_remove_unused_logic {0}
setup_place_and_route -flow ISE -command "Integrated Place and Route" -ignore_keep_hierarchy {0}
setup_place_and_route -flow ISE -command "Integrated Place and Route" -par_ol {high}
setup_place_and_route -flow ISE -command "Integrated Place and Route" -ba_format {VHDL}
setup_place_and_route -flow ISE -command "Integrated Place and Route" -timing_paths_per_constraint {10}
setup_place_and_route -flow ISE -command "Integrated Place and Route" -bits {0}
## Place and Route Settings for Flow 'ISE' Command 'Generate Vendor Constraint File'
setup_place_and_route -flow ISE -command "Generate Vendor Constraint File" -enable_auto_offset_relaxation {0}
setup_place_and_route -flow ISE -command "Generate Vendor Constraint File" -use_ucf_timing_constraints {False}
setup_place_and_route -flow ISE -command "Generate Vendor Constraint File" -no_exec {0}
## Place and Route Settings for Flow 'ISE' Command 'Advanced Options'
setup_place_and_route -flow ISE -command "Advanced Options" -use_pnr_script_cl {0}
setup_place_and_route -flow ISE -command "Advanced Options" -pnr_script_cl {user_pnr_script.tcl}
## Current Place and Route Flow
setup_place_and_route -flow ISE
setup_analysis -clock_frequency
setup_analysis -summary
setup_analysis -num_summary_paths=10
setup_analysis -critical_paths
setup_analysis -num_critical_paths=1
setup_analysis -timing_violations
setup_analysis -net_fanout
setup_analysis -clock_domain_crossing=false
setup_analysis -missing_constraints=false