These tests do not cover all 32 GPIOs as some of them are hardwired for certain functions on the PDMDB. Only those that go to the ECs are covered.
ADC[17,25,7,19] are looped back from SCA DAC[0,1,2,3] therefore should read the value that has been set by the corresponding DAC.
ADC[0,14,20,27] are the current sense readings for input, 1V8, 2V5 and 1V0 respectively.
ADC[13] is connected to the 5k1 precision resistor and should give a reading of around 2000 counts.
ADC[30] measures the RSSI signal so the exact value depends on the optical signal strength measured by the VTRX.
ADC[31] is an internal temperature sensor in the GBT-SCA so the mean will depend on the environmental conditions.
ADC[5] is not used and can be ignored.
The remaining ADC channels are measuring the same fixed voltage and should therefore have about the same mean.
The displayed mean and rms are the unbinned values.
Note: Until 25/11/2019 some of the ADC channels connected to the voltage divider were not correctly configured (current source was enabled but should not have been). For this period the readings for these channels fell into two distinct groups. This is now fixed and they should now all read the same.
This test checks that the 2.5V VDDFE supply is present on each of the EC power pins.
Eye diagrams show the number of sample errors as a function of sampling threshold (vertical axis) against sampling phase (horizontal axis) of the high speed serial UI (unit interval) as measured in the FPGA receiver. Each bin represents the number of errors for this sample.
The larger the central opening, the better the quality of the link. The eye quality depends on many things including the behaviour of the FPGA transceivers so they do not give an absolute measure of the link quality. An eye diagram measured using the PCIe40 FPGA transceiver can be expected to show different behaviour. They do however give an indication of the relative quality.
These plots show, for each of the 6 DTM GBT frames, a summary of the stability of a fixed pattern of 8-bits on each of the 14 e-links (vertical axis) against the phase setting of the e-link (horizontal axis).
A good result is that each horizontal row has at most 2 equally spaced groups of 4 or more consecutive zero (black) bins. Rows with all zero bins are also good.
These values are the phases selected by the automatic GBTX training algorithm that best centre the elink data on the clock edge. They should correspond roughly to the centres of the black regions of the phase scan plots
The table shows the number of bit errors detected for each elink during about 500ms using the trained phase values.