Temperatures read by sensors close to the respective modules.
The numbering of the TCM clock outputs is different to that used on the PDMDB. In the following table tcm_clk0,1,2 are the DTM0,1,2 reference clocks and tcm_clk3,4,5 are the FPGA0,1,2 40MHz clocks
Pass=false in any of the these tests means that at least one GPIO in each tested group has failed.
Expect 128 clocks for each slave select (allow 127).
ADC[0] to ADC[29] are measuring the same fixed voltage and should therefore have about the same mean. ADC[30] measures the RSSI signal so the exact value depends on the optical signal strength measured by the VTRX. ADC[31] is an internal temperature sensor in the GBT-SCA so the mean will depend on the environmental conditions.
The displayed mean and rms are the unbinned values.
These plots show the value of the 4 GBT-SCA DAC outputs as measured by the tester board ADCs. The DACs are set to output the same fixed value so these distributions should have about the same mean and rms.
The displayed mean and rms are the unbinned values.
Eye diagrams show the number of sample errors as a function of sampling threshold (vertical axis) against sampling phase (horizontal axis) of the high speed serial UI (unit interval) as measured in the FPGA receiver. Each bin represents the number of errors for this sample.
The larger the central opening, the better the quality of the link. The eye quality depends on many things including the behaviour of the FPGA transceivers so they do not give an absolute measure of the link quality. An eye diagram measured using the PCIe40 FPGA transceiver can be expected to show different behaviour. They do however give an indication of the relative quality.
These plots show, for each of the 6 DTM GBT frames, a summary of the stability of a fixed pattern of 8-bits on each of the 14 e-links (vertical axis) against the phase setting of the e-link (horizontal axis).
A good result is that each horizontal row has at most 2 equally spaced groups of 4 or more consecutive zero (black) bins. Rows with all zero bins are also good.
Up to and including 25/2/2019 eports 5.0, 5.4, 6.0 and 6.4 were incorrectly configured with the termination resister disabled leading to poor data quality on links 10, 11, 12 and 13 for all DTM GBTXs.
Up to about noon 26/2/2019, the data quality suffers from some buffer corruption because the data are read while samples are still being buffered. This is seen most clearly for GBTX0 which is read first. For this GBTX the bins with errors appear smeared out along the phase axis.
These values are the phases selected by the automatic GBTX training algorithm that best centre the elink data on the clock edge. They should correspond roughly to the centres of the black regions of the phase scan plots
The table shows the number of bit errors detected for each elink during about 500ms.
Up to and including 26/2/2019, these measurements are taken with a fixed e-link phase value of 5, not the values from the GBTX training. After this date the trained phase values are used.