Differences between SctRodDaq_3_0_BRANCH and oxford dev4 (now SR1) local copy
[pcphsctr05] /home/sctroddq/sctsw/RodDaq > cvs diff RodUtils cvs diff: Diffing RodUtils Index: RodUtils/BocTest.cxx =================================================================== RCS file: /afs/cern.ch/user/s/sctpixel/private/cvsroot/RodDaq/RodUtils/BocTest.cxx,v retrieving revision 1.2.2.2 diff -r1.2.2.2 BocTest.cxx 9c9 < #include "../../VmeInterface/RCCVmeInterface.h" --- > #include "RCCVmeInterface.h"
Index: RodUtils/FlashLoad.cxx
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RCS file: /afs/cern.ch/user/s/sctpixel/private/cvsroot/RodDaq/RodUtils/FlashLoad.cxx,v
retrieving revision 1.5
diff -r1.5 FlashLoad.cxx
123c123
< if((rod0->getRevision() == 0xB)||(rod0->getRevision() == 0xC)) {
---
> if(false){//(rod0->getRevision() == 0xB)||(rod0->getRevision() == 0xC)) {
John Hill, I think Index: RodUtils/Makefile =================================================================== RCS file: /afs/cern.ch/user/s/sctpixel/private/cvsroot/RodDaq/RodUtils/Makefile,v retrieving revision 1.5.2.1 diff -r1.5.2.1 Makefile 15a16,18 > -I$(SCTPIXEL_DAQ_ROOT)/CommonWithDsp/Sct \ > -I$(SCTPIXEL_DAQ_ROOT)/commonWithDsp/Pixel \ > -I$(SCTPIXEL_DAQ_ROOT)/Dsp/Common/Include \ 18c21,23 < -I$(DAQ_SW_DIR)/include -I$(DAQ_INCL_DIR) --- > -I$(DAQ_SW_DIR)/include -I$(DAQ_INCL_DIR) \ > -I$(SCTPIXEL_DAQ_ROOT)/Dsp/Common/Include > 21,22c26 < MdspPeek MdspSnap DspPeek TextPeek RegPeek SlvSnap SlvMemPeek AddressList \ < FlashLoadCrate --- > MdspPeek MdspSnap DspPeek TextPeek RegPeek SlvSnap SlvMemPeek AddressList
Index: RodUtils/MdspFlashLoad.cxx =================================================================== RCS file: /afs/cern.ch/user/s/sctpixel/private/cvsroot/RodDaq/RodUtils/MdspFlashLoad.cxx,v retrieving revision 1.2 diff -r1.2 MdspFlashLoad.cxx 103a104,107 > //--JCH Extra > unsigned long int mdspBootMode = 0x1; > //--End JCH extra > 107a112,119 > > //--JCH Extra > cout << "Set Mdsp boot mode to HPI\n"; > //This sets the MDSP to boot from the host port rather than ROM > rod0->hpiLoad(FPGA_CONTROL_REG_REL_ADDR[2], mdspBootMode); > rod0->sleep(1000); > //--End JCH extra > 109c121 < rod0->hpiLoad(FPGA_CONTROL_REG_REL_ADDR[2], mdspReset); --- > rod0->hpiLoad(FPGA_CONTROL_REG_REL_ADDR[2], mdspReset+mdspBootMode);