ChipCounterTest

Part of SctRodDaq

The ASIC, ABCD3T chip has 4 bits of Level1 counter and 8 bits of Bunch Crossing Counter. The idea of this test is to check that the bits in the header of data packets read from the master chips on a module are correct. If there is a counter error, this is considered a reason to take off a module.

The test sends 64 consequtive triggers to the module and reads them back. Only the first 64 bits of the reply are plotted.

The analysis compares the counters from the two links of a module. It also checks to make sure that the counters return non-zero counts.

There are two defects associated with this test: L1_COUNTER and BC_COUNTER that will be reported in the ChipCounterTestResult?. The bit that it failed on is also reported.

ChipCounter? errors do not effect the analog performance of the module. However, it is problematic when the LHC turns on and the module starts sending events advertising to belong to another bunch crossing...

Example raw data plot showing the two counters not in sync: [badcounter]. It can be rather hard to see something like this by eye. Important note: This plot was "generated". This module from Barrel 6 has otherwise good counters. By not sending this module a soft reset for about 10 minutes, you can see that its counters do get out of sync. TW says we send a soft reset every 88 microseconds -- which is the machine revolution period. This is required to avoid problems with loss of syncronization after SEU (single event upsets).

One module on Barrel 5 and one module on Barrel 6 with counter errors has been replaced.