Barrel6ColdTest

A summary of Barrel6 features applicable during the cold test...

B6 Z- ALONE

• NOT TESTED:
  • All modules were tested!

• ADJUSTMENTS:
  • LMT01 Z-4 set TX Current 128 (in response to command reception errors)
  • LMT17 Z-5 set VVCSEL = 4.5V
  • LMT48 Z-1 set VVCSEL = 4.5V
  • LMT52 Z-1 set TX Current 130 (precautionary)

• PECULIARITIES:
  • LMT15 Z-3 20220170200942 channels 286,287 must be masked off to avoid data errors in 3PG test. (NB this fault also shows in full NMask test.)

• MISSING CHIPS:
  • LMT08 Z-2 20220330200606 - modified module reading 11 chips
  • LMT30 Z-5 20220330200693 - modified module reading 11 chips
  • We will be able to read 12 chips from all modified modules after the "ErrorMask?" feature of the DAQ has been fully debugged.

• Useful Run List:
  • tbc

B6 Z+ ALONE

• NOT TESTED:
  • LMT12 Z+5 - did not hold detector bias voltage. Module was replaced after the cold test.
  • LMT31 Z+2 - cabling or PS fault. Module tested OK after the cold test using a different PS channel/cable.
  • LMT39 Z+1 - VccSense? fault. This was later found to be downstream of the TPP. Repair to be made at CERN. </ib>

• PARTIALLY TESTED
  • LMT28 Z+1 is a modified module. Even tested over a range of different TX and RX settings, it continues to cause errors at Bin 14 of a NO scan, causing the scan to abort for the associated ROD. The error log would suggest that the module has caused BC errors, but since it gives the same error for every module on the ROD I'm not sure this is meaningful (PWP). In any case, bin 14 is at very low threshold, well below the normal operating point, and the module works correctly at higher thresholds - so we'll leave this one on the barrel.

• ADJUSTMENTS:
  • LMT20 Z+1 set VVCSEL 3.0V
  • LMT20 Z+2 set VVCSEL 3.5V
  • LMT27 Z+1 set VVCSEL 3.5V
  • LMT27 Z+2 set TX Current 140 (in response to command reception problems)
  • LMT29 Z+1 set VVCSEL 3.0V
  • LMT32 Z+3 set VVCSEL 3.5V
  • LMT51 Z+4 set TX Current 130 (precautionary)
  • LMT51 Z+5 set TX Current 130 (precautionary)
  • LMT55 Z+3 set TX Current 130 (precautionary)
  • LMT47 Z+3 set TX Current 200 (due to BC errors)
  • LMT28 Z+1 set TX Current 192 (due to BC errors)
  • LMT10 Z+5 set TX Current 192 (due to BC errors)
  • plus several RX threshold tweaks
• PECULIARITIES:
  • LMT11 Z+5 chip S10 power on resetcircuit does not work, at least with our present start up regime. Hard Reset must be sent before this chip will return valid data.
  • LMT35 Z+1 no analogue response - seems VccSense? connection has failed
  • LMT48 Z+1 20220040200550 channel 448 must be masked off to avoid data errors in 3PG test (found by binary search)
  • LMT28 Z+1 UK117, which is a modified module, had to be taken out of the configuration because it was causing data errors in NO.

• MISSING CHIPS:
  • LMT09 Z+2 20220330200209 - modified module reading 11 chips
  • LMT17 Z+5 20220330200505 - modified module reading 11 chips
  • LMT19 Z+3 20220170200932 - VCSEL death, broken VDC bond or fibre break occuring after the harness test => reading 11 chips
  • LMT28 Z+1 20220330200117 - modified module reading 11 chips
  • We will be able to read 12 chips from all modified modules after the "ErrorMask?" feature of the DAQ has been fully debugged.

• Useful Run List:
  • 5779-0 QuickNMask?
  • 5779-1 SD completes without errors
  • 5779-2 3PG completes without error
  • 5779-5 NO completes despite errors, bin 13, ROD 18 sdsp 2 (LMT 27 or 28)
  • 5779-6 DTN completes without errors
  • 5813-0 NMask completes without errors
  • 5813-1 NO completes without errors! :)
  • 5813-2 DTN --later discovered that it was done using wrong trigger.
  • 5813-3 SyncTN? :)
  • 5813-4 3PG (note: without an SD before it) :)
  • 5813-7 SD

B6 Complete

• NOT TESTED:
  • LMT12 Z+5 - did not hold detector bias voltage. Module was replaced after the cold test.
  • LMT31 Z+2 - cabling or PS fault. Module tested OK after the cold test using a different PS channel/cable.
  • LMT35 Z+1 - cabling or PS fault. Module tested OK after the cold test using a different PS channel/cable.
  • LMT39 Z+1 - VccSense? fault. This was later found to be downstream of the TPP. Repair to be made at CERN.

• PARTIALLY TESTED:
  • LMT11 Z+5 lk1 - S10 prone to errors. Sometimes would work OK, at other times it would not. Sometimes HR would help, sometimes it would not. We ended up switching this chip off.
  • LMT01 Z-6
    • Coincident with improved airflow in the ROD rack from ~4pm on 26/05, this module started to give occasional errors. This was traced to an increased PIN current, coincident with the start of the improved airflow. With effect 27/05 the TX current was reduced, and the problem went away.
  • LMT28 Z+1 lk1
    • modifed module, causes errors in bin 14 of NO test if both sides read through one link - hence excluded from some tests.
  • LMT44 Z-5
    • clock/command reception not 100% reliable. If the module started in the "working" state, it would continue to work. If it did not start in the working state, we were often unable to recover it. For the last day's running, we moved to SELECT=1 for this module, which worked reliably. Not fully understood.

• LGS (Large Gain Spread) candidates from (half barrel) 3PG tests:
  • LMT02 Z+2 20220170200879 chip S12 gain rms 3.5
    • cold test xml file with modified shaper settings downloaded from SCTDB
    • Module OK
  • LMT03 Z-1 20220040200459 chip S4 gain rms 3.4
    • cold test xml file with modified shaper settings downloaded from SCTDB
    • Module OK
  • LMT10 Z+5 20220040200377 chip S10 gain rms 4.3
    • cold test xml file with modified shaper settings downloaded from SCTDB
    • the new file's chip addresses were initially set up for SELECT=1, hence it did not work right away, but this was corrected by PWP.
    • Module OK
  • LMT23 Z+5 20220380200140 chip E13 gain rms 5.4
    • Module cold tested with SCTDAQ predating xml file generation :-(
    • Oxford file modified to set 20microA shaper for this chip from run 5882.
    • Gain now uniform, although trimming not correct.
    • Module OK
  • LMT32 Z-3 20220170200832 chip M0 gain rms 4.4
    • cold test xml file with modified shaper settings downloaded from SCTDB
    • Module OK
  • LMT40 Z-5 20220040200137 chip S11 gain rms 5.5
    • Module cold tested with SCTDAQ predating xml file generation :-(
    • Oxford file modified to set 20microA shaper for this chip from run 5882.
    • Gain now uniform, although trimming not correct.
    • Module OK
  • LMT45 Z+2 20220170200967 chip S12 gain rms 5.8
    • cold test xml file with modified shaper settings downloaded from SCTDB
    • Module OK
  • LMT47 Z-1 20220380200150 chip S9 gain rms 5.5
    • No cold data set xml file available for this module
    • Oxford file modified to set 20microA shaper for this chip from run 5882.
    • Module OK
  • LMT52 Z+3 20220170200701 chip S12 gain rms 3.8
    • cold test xml file with modified shaper settings downloaded from SCTDB
    • Module OK

• Useful Run List
  • RUN 5815: 666 modules
    • 5815-0 RxThreshold
  • RUNS 5852-5857: 662 modules
    • 5852-0 StrobeDelayTest
    • 5852-1 ThreePointGain?
    • 5852-4 NoiseOccupancy?
    • 5857-0 NoiseOccupancy? - no errors
    • 5857-1 DoubleTriggerNoise (reading "wrong" bin)
  • RUNS 5872-5875: 666 + (2 * 0.5) modules
    • 5872-0 QuickNMask? - no errors
    • 5872-1 PipelineTest - no errors
    • 5873-0 StrobeDelayTest - no errors
    • 5873-1 ThreePointGain? - completes without errors but analysis fails due to IPC timeout. Offline, missing 3rd scan point. Archiving service didnt finish?
    • 5874-0 NoiseOccupancy? - no errors
    • 5874-1 DoubleTriggerNoise - no errors
    • 5875-0 StrobeDelayTest - no errors
    • 5875-1 ThreePointGain? - ROD1 aborts scan 3/3 bin 38/40, but data valid
  • RUN 5882: reduced set of modules, but includes 3 BLG candidates for which manual shaper current adjustments had now been made.
    • 5882-2 StrobeDelayTest - no errors
    • 5882-3 ThreePointGain? - no errors
  • RUNS 5908-5913: 664 + (0.5) modules
    • 5908-0 DoubleTriggerNoise (reading correct bin)
    • 5913-0 SynchTriggerNoise (R3 version - 1E6 events at 1.0fC)
    • 5913-1 SynchTriggerNoise (R3 version - 2E5 events at 0.9fC)

Final list of non standard DAQ settings

tbc

Final list of non standard PS settings

• LMT02 Z+1 VVCSEL = 5.0V
• LMT02 Z+6 VVCSEL = 5.0V
• LMT03 Z-5 SELECT = 1
• LMT05 Z+6 VVCSEL = 5.0V
• LMT12 Z-1 VVCSEL = 3.0V
• LMT12 Z-6 VVCSEL = 5.0V
• LMT17 Z-5 VVCSEL = 4.5V
• LMT29 Z+1 VVCSEL = 3.5V
• LMT32 Z+3 VVCSEL = 3.5V
• LMT38 Z+2 VVCSEL = 3.0V
• LMT44 Z+1 SELECT = 1

After the Cold Test

Three modules were replaced:

• LMT08 Z+5
  • 20220330200258 was removed because the bottom side bias connection failed during the cold test
  • 20220330200728 was its replacement
• LMT11 Z+5
  • 20220170200916 was removed because chip S10 did not work reliably
  • 20220330200747 was its replacement
• LMT12 Z+5
  • 20220040200129 was removed because its detectors could not be biassed
  • 20220040200518 was its replacement

Each of the replacement modules, and their immediate neighbours, tested OK

The sense connections of three modules were checked by DVM at the TPP:

• LMT31 Z+2 was OK
• LMT35 Z+1 was OK
• LMT39 Z+1 Vcc to VccSense? was measured at 187 ohms => FAULT
  • Most probably a solder repair is needed to connect these two lines at PPB1.
  • This was not done at Oxford and must therefore be done at CERN.

Two modules, which could not be powered during the cold test, were retested:

• LMT 31 Z+2
  • still did not work with cable 17-05-02-2 (CR09 CH07)
  • tested successfully with cable 17-05-02-3 (CR09 CH08)
• LMT 35 Z+1
  • not retested with cable 17-05-06-1 (CR09 CH30)
  • tested successfully with cable 17-05-06-2 (CR09 CH31)

Offline

• LMT18 Z+2 shows noise/offsetslope for last two chips. Try SELECT=1 for this module or one or its near neighbours.