The definitive list of known exceptions
- lmt01 Z+6 20220330200024
- No redundant TTC (from harness test)
- lmt03 Z-5 20220330200357
- No redundant TTC (from harness test)
- lmt03 Z+6 20220330200319
- Noise slope in last 4 chips
- lmt05 all
- Harnesses not tested at Oxford
- lmt06 all
- Harnesses not tested at Oxford
- lmt07 Z+6 20220040200090
- No redundant TTC (from harness test)
- lmt08 Z+1 20220330200472
- Channel 722 had to be masked off in order to get the ROD to process its (analogue test) data. Looks as if the data compression does not work correctly for this channel.
- lmt11 Z-2 20220330200341
- One warm NO has high OPE at >1fC, lower face
- lmt11 Z+6 20220330200353
- No redundant TTC (from harness test)
- One warm NO has high OPE at >1fC, chip S12
- lmt16 Z-6 20220330200295
- On 04-11-04, exhibited MD at 350V, although had been OK before
- lmt17 Z+2 20220330200287
- VDDretsense o/c on harness, now linked to VDDreturn at PP1.
- VCCsense o/c on harness, now linked to VCC at PP1.
- For this module, use VCC 3.7V and VDD 4.1V.
- lmt17 Z+6 20220330200292
- VCCsense o/c on harness, now linked to VCC at PP1.
- For this module, use VCC 3.7V.
- VCCsense o/c on harness, now linked to VCC at PP1.
- lmt18 Z+2 20220330200267
- Channel 1148 had to be masked off in order to get the ROD to process its (analogue test) data. Looks as if the data compression does not work correctly for this channel.
- lmt21 Z-6 20220040200324
- Slightly high current (1.53µA@200V, 1.87µA@500V)
- One cold NO has high OPE at > 1fC, chip S11
- lmt24 Z+3 20220330200446
- With SELECT=0, an offset slope is apparent across the last few chips. The NO is also increased in this region. With SELECT=1, the module is OK.
- For this module, use SELECT =1.
- With SELECT=0, an offset slope is apparent across the last few chips. The NO is also increased in this region. With SELECT=1, the module is OK.
- lmt28 Z+6 20220380200139
- Link 1 VCSEL is “Very Sick”: signal amplitude varies sharply at the start of each event. Error free operation could not be achieved during the cold test. Use redundancy instead.
- For this module, read 11 chips through link 0.
- Link 1 VCSEL is “Very Sick”: signal amplitude varies sharply at the start of each event. Error free operation could not be achieved during the cold test. Use redundancy instead.
- lmt29 Z-3 20220380200111
- Link 1 dead – use redundancy. (Yes really, link 0 is OK)
- For this module, read 11 chips through link 0.
- Link 1 dead – use redundancy. (Yes really, link 0 is OK)
- lmt30 Z-6 20220170200008
- Shows noise slope if neighbour set to SELECT=0
- lmt30 Z-5 20220170200009
- Use SELECT=1 to avoid noise slope on neighbour
- For this module, use SELECT =1.
- Use SELECT=1 to avoid noise slope on neighbour
TODO: add channels with anomalous RX threshold settings
Things that can be "made better" if we feel like it
There two stuck pipeline cells, which in theory could be suppressed on the ROD, but this hasn't been implemented.- Module 20220040200500, link0 channel 672
- Module 20220330200190, link0 channel 454
What does this mean for configuration files?
For optimum performance, four exceptions must be accomodated in the relevant module configuration files:
- lmt08 Z+1 20220330200472
- one channel masked off, channel 722 (channel 82 of chip E5)
20220330200472.xml
<chip id="05" address ="0x25" active="1"> ... <mask>0xffffffff 0xfffbffff 0xffffffff 0xffffffff</mask>
- lmt18 Z+2 20220330200267
- one channel masked off, channel 1148 (channel 124 of chip S10)
20220330200267.xml
<chip id="08" address ="0x2a" active="1"> ... <mask>0xefffffff 0xffffffff 0xffffffff 0xffffffff</mask>
- lmt28 Z+6 20220380200139
- read 11 chips through link 0
20220380200139.xml
... <chip id="05" address ="0x25" active="1"> <config> 1 3 0 0 0 0 1 0 1 0 1</config> ... <chip id="06" address ="0x28" active="1"> <config> 1 3 0 0 0 0 0 0 0 1 1</config> ... <chip id="07" address ="0x29" active="1"> <config> 1 3 0 0 0 0 0 1 1 0 1</config> ...
- lmt29 Z-3 20220380200111
- read 11 chips though link 0
20220380200111.xml
... <chip id="05" address ="0x25" active="1"> <config> 1 3 0 0 0 0 1 0 1 0 1</config> ... <chip id="06" address ="0x28" active="1"> <config> 1 3 0 0 0 0 0 0 0 1 1</config> ... <chip id="07" address ="0x29" active="1"> <config> 1 3 0 0 0 0 0 1 1 0 1</config> ...
Two exceptions must be accomodated in both the relevant module configuration files and in the power supply section of the master configuration file:
- lmt24 Z+3 20220330200446
- Set Select =1
20220330200446.xml
<select>1</select>
Barrel3.xml
<channel id="XX" MUR="3124" module="3"> <state name = "OFF"> <param name="LVCLKS" value="1"></param> </state> <state name = "STB"> <param name="LVCLKS" value="1"></param> </state> <state name = "ON"> <param name="LVCLKS" value="1"></param> </state> </channel>
- lmt30 Z-5 20220170200009
- Set Select = 1
20220170200009.xml
<select>1</select>
Barrel3.xml
<channel id="XX" MUR="3030" module="5"> <state name = "OFF"> <param name="LVCLKS" value="1"></param> </state> <state name = "STB"> <param name="LVCLKS" value="1"></param> </state> <state name = "ON"> <param name="LVCLKS" value="1"></param> </state> </channel>
Two exceptions must be accomodated in the power supply section of the configuration file only:
- lmt17 Z+2 20220330200287
- For this module, use VCC 3.7V and VDD 4.1V.
Barrel3.xml
<channel id="XX" MUR="3117" module="6"> <state name = "ON"> <param name="LVch_Vcc" value="3.7" loAlarm="0.0" loWarn="3.6" hiWarn="3.8" hiAlarm="3.9"></param> <param name="LVch_Vdd" value="4.1" loAlarm="0.0" loWarn="4.0" hiWarn="4.2" hiAlarm="4.3"></param> </state> </channel>
- lmt17 Z+6 20220330200292
- For this module, use VCC 3.7V.
Barrel3.xml
<channel id="XX" MUR="3117" module="6"> <state name = "ON"> <param name="LVch_Vcc" value="3.7" loAlarm="0.0" loWarn="3.6" hiWarn="3.8" hiAlarm="3.9"></param> </state> </channel>
Chips not read out during the B3 cold test at Oxford
For Barrel3Analysis, the following chips were missing during data taking.
Position Serial Number Chip(s) Masked Reason -->later? LMT08 Z+1 20220330200472 M0 or M0-E5 Data errors -->solved by masking off 1 channel LMT22 Z+5 20220440200373 M0 Link0 no data at end of run --> recovered later LMT28 Z+6 20220380200139 M8 Link1 VCSEL “very sick” LMT29 Z-3 20220380200111 M0 Link1 known fibre break LMT31 Z+2 20220040200245 M8 BC/L1A counter errors --> module replaced
MissingLinks: a complete list of known dead data links and the locations of modified modules for all barrels is available here.