00001 /* 00002 * sct_structures.h 00003 * 00004 * A fresh look at what may be needed for the 00005 * SCT ROD configuration data structures 00006 * 00007 * This is a revised and expanded version of John Hill's "sct_structure.h" 00008 * which can be found here: 00009 * http://sctpixel.home.cern.ch/sctpixel/Cambridge/sct_structure.txt 00010 * 00011 * From our point of view, the layout of the structures is less important 00012 * than their content, so the ROD developers should feel free to suggest 00013 * alternative layouts and/or naming schemes. 00014 * 00015 * Version 0.8 PWP/GFM 2002.06.04 00016 * Version 1.0 PWP 2002.06.17 00017 * Version 1.1 PWP 2003.03.25 00018 * Version 1.2 DPSF 2003.03.27 00019 */ 00020 #include "processor.h" 00021 #include "bocStructure.h" 00022 00023 #ifndef SCT_STRUCT_H /* multiple inclusion protection */ 00024 #define SCT_STRUCT_H 00025 00026 #define N_SCT_MODULES 48 /* 48 modules directly attached +12 modules */ 00027 #define N_SCT_EXTMODULES 12 /* using redundant command links OFF ROD */ 00028 #define N_SCT_TOTMODULES ((N_SCT_MODULES)+(N_SCT_EXTMODULES)) 00029 00030 #define N_SCT_CHANS 128 00031 #define N_SCT_CHIPS 12 00032 00033 /* Default & off-ROD positions of a module's TTC fibres. The default primary 00034 TTC fibre location for a module is simply the module's position inside the 00035 structure set. */ 00036 #define DEFAULT_PTTC 0x80 00037 #define OFF_ROD_TTC 0xff 00038 /* Structure Definitions */ 00039 typedef struct { 00040 00041 /* This structure corresponds to the ABCD chip configuration register. 00042 * Aside from one correction to suit the ABCD3T chip (trimRange) it 00043 * is essentially the same as that proposed by John Hill. */ 00044 00045 UINT16 readoutMode : 2; 00046 UINT16 calibMode : 2; 00047 UINT16 trimRange : 2; 00048 UINT16 edgeDetect : 1; 00049 UINT16 mask : 1; 00050 UINT16 accumulate : 1; 00051 UINT16 inputBypass : 1; 00052 UINT16 outputBypass : 1; 00053 UINT16 master : 1; 00054 UINT16 end : 1; 00055 UINT16 feedThrough : 1; 00056 UINT16 padding : 2; /*pad to 16 bits */ 00057 00058 } ABCDConfig; 00059 00060 typedef struct{ 00061 00062 /* This structure holds calibration information about this 00063 * ABCD chip. None of these parameters was present in 00064 * John Hill's version - we probably hadn't thought of it 00065 * two years ago! */ 00066 00067 /* We store a functional representation of the response 00068 * curve (equivalent threshold as a function of charge) 00069 * so that we may request ROD to set the threshold to 00070 * a value specified in fC. */ 00071 00072 UINT8 rc_function; /* Used to denote the type of function which 00073 * has been fitted to the response curve, eg. 00074 * 0 - no calibration information 00075 * 1 - (can't remember, probably exponential) 00076 * 2 - second order polynomial 00077 * 3 - (can't remember, probably "Grillo" func) 00078 * 4 - straight line fit */ 00079 FLOAT32 rc_params[3]; /* Response Curve Fit */ 00080 00081 FLOAT32 c_factor; /* Capacitor Correction factor */ 00082 00083 UINT32 unused[3]; /* For data alignment */ 00084 /* Other calibration data is available from the wafer test - 00085 * but it's probably irrelevant. */ 00086 00087 /* We had a discussion about putting temperature correction 00088 * coefficients in here, but to avoid the complication of 00089 * delivering recent temperature data to ROD, we conclude 00090 * that temperature corrections are best done offline. */ 00091 00092 } ABCDCaldata; 00093 00094 typedef struct { 00095 00096 /* All registers except the TrimDAC registers. The contents of 00097 * these registers change more often than the TrimDAC settings 00098 * and will most often be loaded as a group. */ 00099 00100 ABCDConfig config; /* Configuration Register 16 bits */ 00101 00102 UINT16 unused; /* For data alignment */ 00103 UINT8 vthr; /* Threshold, 8 bits */ 00104 UINT8 vcal; /* Calibration Amplitude, 8 bits */ 00105 UINT8 delay; /* Strobe Delay, 6 bits */ 00106 UINT8 preamp; /* Preamp Bias Current, 5 bits */ 00107 UINT8 shaper; /* Shaper Current, 5 bits */ 00108 00109 UINT32 mask[4]; /* Mask Register, 128 bits */ 00110 } ABCDBasic; 00111 00112 typedef struct { 00113 00114 /* This structure includes all register settings and 00115 * calibration information for one ABCD chip. */ 00116 00117 UINT8 active; /* 1 -> participates in scans */ 00118 /* 0 -> register contents unchanged during scanning 00119 * (although the fixed values are still loaded) */ 00120 UINT8 address; /* In SCTDAQ we chose to associate a hardcoded 00121 * chip address with each location on a module. 00122 * That's fine as long as things work correctly. 00123 * If we allow the address to be configurable 00124 * we can recover from (a subset of possible) 00125 * address failure modes. */ 00126 00127 UINT8 unused; /* For data alignment */ 00128 00129 UINT8 target; /* <= I think this should be correct? */ 00130 00131 ABCDBasic basic; /* All registers apart from the TrimDACs */ 00132 00133 ABCDCaldata caldata; /* Calibration data for this chip */ 00134 00135 UINT8 trim[N_SCT_CHANS]; /* TrimDAC registers, 4 bits/channel 00136 * This could be more tightly packed, but 00137 * unless you need the space, this sounds 00138 * like an unnecessary complication... */ 00139 00140 } ABCDChip; 00141 00142 00143 typedef struct { 00144 00145 /* This structure includes all register settings and 00146 * calibration information for one ABCD module. */ 00147 00148 ABCDChip chip[N_SCT_CHIPS]; 00149 00150 UINT8 present; /* Module is physically present. Does not need setting 00151 externally; handled by the Master DSP. */ 00152 00153 UINT8 active; /* 1 -> participates in scans */ 00154 /* 0 -> registers unchanged during scanning */ 00155 UINT8 select; /* 1 -> use redundant clk/com; ID4=1 */ 00156 /* 0 -> use primary clk/com; ID4=0 */ 00157 00158 UINT8 groupId; /* The ID of the module's group. This is used to indicate 00159 which slave DSP will receive the module's data (if group 00160 based distribution is set), and also to allow different 00161 module groups to be triggered independently (for 00162 cross-talk studies). Valid range: [0,7] */ 00163 00164 BOCConfig *bocConfig; /* Pointer to the BOC configuration structure. 00165 Does not need setting externally; handled by the MDSP. */ 00166 UINT8 pTTC; /* primary TX channel (used when SELECT = 0) */ 00167 UINT8 rTTC; /* redundant TX channel (used when SELECT = 1) */ 00168 00169 UINT8 rx[4]; /* data links used by module: SCT: 0,1 Pixel 0, 0 & 1, or all. */ 00170 00171 UINT8 unused1[2]; 00172 UINT32 unused2[3]; /* align module structures on 8 word boundary */ 00173 00174 /* Each of a module's RX datalinks may or may not be in use 00175 * dependent upon the bypass configuration. ROD should 00176 * consider the settings of the MASTER bit of the 00177 * configuration register of each master chip when 00178 * choosing to enable or disable input streams, 00179 * reallocating buffers as necessary. */ 00180 00181 } ABCDModule; 00182 00183 #endif /*SCT_STRUCT_H */