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ABCDchip.h

00001 /******************************************************************************
00002  * 
00003  *  Title  : ABCDcommands.h  ==> ABCDchip.h, ABCDfxn.h
00004  *  Version: 15 June 2002
00005  *   
00006  *  Description:  
00007  *  Related files: ABCDcommands.c
00008  *  Documentation: http://s.home.cern.ch/s/sct/public/sctdaq/sctdaq.html
00009  *
00010  *  Author: Lukas Tomasek, tomasekl@fzu.cz
00011  *
00012  *  modifications/bugs:
00013  *
00014  *  Merged in the definitions from ABCDconfig.h                  14.01.03 dpsf
00015  ******************************************************************************/
00016 
00017 #ifndef ABCD_CHIP_H    /* multiple inclusion protection */
00018 #define ABCD_CHIP_H
00019  
00020  /* chip address (bits 5:4) */
00021 #define PRIMARY_FIBRE     0x2
00022 #define ADJACENT_FIBRE    0x3
00023 /* chip address (bits 3:0) */ 
00024 #define ALL_CHIPS         0x3F   
00025 #define CHIP_ADDR_LOOP    0xFF    
00026 
00027 #define M0_CHIP          0x0
00028 #define S1_CHIP          0x1  
00029 #define S2_CHIP          0x2  
00030 #define S3_CHIP          0x3  
00031 #define S4_CHIP   0x4  
00032 #define E5_CHIP   0x5  
00033 #define M8_CHIP   0x8  
00034 #define S9_CHIP   0x9 
00035 #define S10_CHIP  0xA  
00036 #define S11_CHIP  0xB  
00037 #define S12_CHIP  0xC  
00038 #define E13_CHIP  0xD  
00039 
00040 /* full chip address (bits 5:0) */
00041 #define CHIP_ADDRESS(fibre, addressBits3to0) (((fibre)<<4)|(addressBits3to0))
00042 
00043 
00044 #define CHIP_ALLCHIPS_ADDR_CONSTRUCT  0xf
00045 
00046 /* readout mode */
00047 #define RM_HIT     0x0   /* detector alignment */
00048 #define RM_LEVEL   0x1   /* normal data taking */ 
00049 #define RM_EDGE    0x2   /* normal data taking */
00050 #define RM_TEST    0x3   /* test mode */
00051 
00052 /* calibration mode */
00053 #define CAL_IN3      0x0  
00054 #define CAL_IN2      0x1  
00055 #define CAL_IN1      0x2
00056 #define CAL_IN0      0x3
00057 
00058 /* trim DAC range */
00059 #define TRIM_DAC_RANGE_60mV    0x0
00060 #define TRIM_DAC_RANGE_120mV   0x1  
00061 #define TRIM_DAC_RANGE_180mV   0x2  
00062 #define TRIM_DAC_RANGE_240mV   0x3
00063 
00064 /* command length in bits */
00065 #define L1_TRIGGER_LENGTH  3
00066 #define FAST_CMD_LENGTH    7
00067 #define SLOW_CMD_LENGTH   27
00068 #define DATA_CMD_LENGTH   64
00069 #define MASK_CMD_LENGTH  192
00070 
00071 #define NO_CMD           100
00072 
00073 typedef enum { 
00074 L1_TRIGGER    =101,
00075 SOFT_RESET    =102,
00076 BC_RESET    =103
00077 } FAST_CMD_ID;
00078 
00079 typedef enum { 
00080 PULSE_INPUT_REG     =104,
00081 ENABLE_DATA_TAKING  =105, 
00082 CALIBRATION_PULSE   =106
00083 } SLOW_CMD_ID;
00084 
00085 typedef enum {
00086 CONFIG_REG         =107,
00087 STROBE_DELAY_REG   =108, 
00088 THRESHOLD_REG      =109, 
00089 BIAS_DAC_REG       =110,  
00090 TRIM_DAC_REG       =111 
00091 } DATA_CMD_ID;
00092 
00093 typedef enum {
00094 DELAY              =112,
00095 MASK               =113
00096 } EXTRA_CMD_ID;
00097 
00098 /* maximum length of a command stream to configure one module= 3240 words= 0xca8;
00099    a small amount of padding is added. */
00100 #define CMD_STREAM_WMAX 0xd00
00101 
00102 struct CMD_BUFF {
00103 UINT32 *data;                      /* command stream buffer */
00104 unsigned int bufferSizeWords; /* word is 32bits wide */
00105 unsigned int bitIndex; /* current write bit index (number of full bits in the data buffer) */
00106 unsigned char inUse;
00107 };
00108 
00109 #define WORD_INDEX(bitIndex) ((bitIndex)/32) /* returns 32bit word index */
00110 
00111 
00112 /* merged from ABCDconfig.h */
00113 typedef enum {
00114   MISSING = 0,
00115   DEAD = 1,
00116   END = 2,
00117   MASTER = 3,
00118   SLAVE = 4,
00119   LONELY = 5,
00120   PARANOID = 6
00121 } ABCD_ROLES;
00122 
00123 
00124 
00125 #endif /* ABCD_CHIP_H */

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