00001 /************************************************************************************* 00002 * memoryPartitions.h 00003 * 00004 * synopsis: Defines the memory partitions in the DSP memory space. 00005 * Declares routine for initializing memory. 00006 * Should be included in the DSP and the VME host code. 00007 * 00008 * related files: 00009 * The configuration database file for the project, e.g. rodRunBios.cdb 00010 * 00011 * In Project->Options->Compiler it is POSSIBLE to define 00012 * TI_EVM: EVM DSP has smaller SDRAMs than the ROD DSPs. This option partitions 00013 * memory accordingly. 00014 * MAP_0: probably never used, ROD DSPs are wired for MAP_1, see peripherals 00015 * manual 10-5 00016 * EMULATE_HOST: If defined, handles both sides of the list processing handshake. 00017 * 00018 * Damon Fasching, UW Madison fasching@wisconsin.cern.ch 00019 * Douglas Ferguson, UW Madison (510) 486-5230 dpferguson@lbl.gov 00020 * 00021 * modifications/bugs 00022 * - Updated to reflect changes in the project organization. When BIOS was 00023 * introduced, the program memory sections must be defined inside the config 00024 * database; the MEMORY section of the linker command file is no longer used & 00025 * is taken out. External code & data are combined and put the XPROG memory 00026 * section (FARDATA gone). The default positions and sizes of the 4 text, and 00027 * the primitive & reply buffers, have changed. 6701s now have 32M of external 00028 * memory; 6201 still has 16M. 26.04.02 dpsf 00029 * 00030 * - Inter-DSP communication buffers put in SDRAM & communication registers moved 00031 * to the beginning of internal memory (IDREG segment in the configuration 00032 * database file) The 2 handshake registers have been left in internal memory 00033 * with the other registers. A new section of memory, IDATA, has been created 00034 * for important program variables; they should now remain relatively fixed in 00035 * one spot instead of floating about in the program IDRAM while code is added 00036 * & modified, as they did before. This is intended to be used with the 00037 * DATA_SECTION pragma (see Optimizing C Compiler User's Guide, 7.6.4). Use of 00038 * the pragma makes variables inaccessible to routines in other files, so 00039 * use with care. (They can still be accessed by calling a function to return a 00040 * pointer to them). 05.06.02 dpsf 00041 * 00042 * - Added EXPERT, HCMD, HSTAT, TRAPREQ & TRAPSTAT registers for general purpose 00043 * use, histogramming, and event trapping respectively. New defined locations in 00044 * memory were added for the (suggested) base in memory of histograms & the 00045 * trapping buffer as well. 20.06.02 dpsf 00046 * 00047 * - New memory section MODULE_DATA was added for storage of new module 00048 * configuration structures on the master. 03.07.02 dpsf 00049 * 00050 * modifications/bugs 00051 * - Master & slave DSPs now have different size primitive & reply buffers. The 00052 * compilation constants HOST_(PRM/REP)_BFR_(BASE/SZ) in memoryPartitions.h have 00053 * been replaced with different sets for the two DSP types. 10.12.02 dpsf 00054 ************************************************************************************* 00055 * NOTE: The segment sizes defined in this file for use in positioning registers and 00056 * other program items (which are not explicitly declared as variables) must 00057 * agree with the corresponding memory segment length and base, set in the 00058 * configuration database file (.cdb). **Otherwise overwrites are possible** The 00059 * memory order of the segments defined there should be maintained as well. These 00060 * segment sizes are: 00061 * 00062 * IDREGS_SZ, IDATA_SZ, IDRAM_MEM_SZ, BURST_SZ, XPROG_SZ, and 00063 * (master only) MODULE_DATA_SZ 00064 * 00065 * IDRAM_SZ is the total size of the DSP IDRAM. 00066 * (IDRAM_MEM is used here for the memory section IDRAM in the .cdb file, which 00067 * cannot be renamed.) 00068 ************************************************************************************/ 00069 #ifndef MEMORY_PARTITIONS 00070 #define MEMORY_PARTITIONS 00071 00072 #include "processor.h" 00073 /* 00074 * Each DSP has 0x10000 bytes of internal program memory, IPRAM, starting at 0x0 00075 * 0x10000 bytes of internal data memory, IDRAM, starting at 0x80000000 00076 * 0x1000000 bytes SDRAM starting at 0x2000000 or 0x3000000 00077 * 00078 * Some of this is used for buffers and communication mailboxes whose addresses and 00079 * sizes are defined below. 00080 * 00081 * Memory sections are defined in the configuration database file so that it is 00082 * available for the linker to allocate code, data, stack, heap, etc... The BIOS is 00083 * set up so that it uses an external user linker command file (.cmd) for the 00084 * placement of non-BIOS related memory sections; this file then calls the BIOS .cmd 00085 * file at its finish. 00086 * 00087 * table of available memory spaces 00088 * 00089 * mem space base address what's there for each device 00090 * 00091 * MAP 0 MAP 1 EVM master DSP slave DSPs 00092 * EMIF CE0 0x00000000 0x00400000 256KB SBSRAM RRI FPGA external registers 00093 * EMIF CE1 0x01000000 0x01400000 boot ROM router 00094 * EMIF CE2 0x02000000 0x02000000 4MB SDRAM 16MB SDRAM 16MB SDRAM 00095 * EMIF CE3 0x03000000 0x03000000 4MB SDRAM 16MB SDRAM 00096 * IPRAM 0x01400000 0x00000000 64KB internal program memory 00097 * IDRAM 0x80000000 0x80000000 64KB intermal data memory 00098 * 00099 ************************************************************************************* 00100 * sizes of the available memories. 00101 ************************************************************************************/ 00102 #define IPRAM_SZ (0x10000) /* 64KB of internal program memory */ 00103 #define IDRAM_SZ (0x10000) /* 64KB of internal data memory */ 00104 00105 #ifdef TI_EVM 00106 #define SDRAM0_SZ (0x400000) /* 4MB of SDRAM available at CE2 on the EVM */ 00107 #define SDRAM1_SZ (0x400000) /* 4MB of SDRAM available at CE3 on the EVM */ 00108 00109 #else 00110 #if (defined(I_AM_MASTER_DSP) || defined(I_AM_NT_HOST) || defined(I_AM_LINUX_HOST)) 00111 #define SDRAM0_SZ (0x800000) /* 16 MB of SDRAM available on the ROD */ 00112 #define SDRAM1_SZ (0x800000) /* divided into two modules both at CE2 */ 00113 #elif (defined(I_AM_SLAVE_DSP)) 00114 #define SDRAM0_SZ (0x1000000) 00115 #define SDRAM1_SZ (0x1000000) 00116 #endif 00117 #endif 00118 00119 /************************************************************************************ 00120 * base addresses the available memories 00121 ************************************************************************************/ 00122 /* internal program, internal data and 4 EMIF chip enables for off chip memories */ 00123 #ifdef MAP_0 00124 #define CE0_BASE (0x00000000) 00125 #define CE1_BASE (0x01000000) 00126 #define IPRAM_BASE (0x01400000) 00127 #else 00128 #define CE0_BASE (0x00400000) 00129 #define CE1_BASE (0x01400000) 00130 #define IPRAM_BASE (0x00000000) 00131 #endif 00132 00133 #define CE2_BASE (0x02000000) 00134 #define CE3_BASE (0x03000000) 00135 #define IDRAM_BASE (0x80000000) 00136 00137 /* SDRAM: EVM has 2 4MB SDRAMs at CE2 and CE3; ROD has 16 MB SDRAM at CE2 00138 + another 16M at CE3 for 6701s */ 00139 #define SDRAM0_BASE (CE2_BASE) 00140 #ifdef TI_EVM 00141 #define SDRAM1_BASE (CE3_BASE) 00142 #else 00143 #if (defined(I_AM_MASTER_DSP)|| defined(I_AM_NT_HOST) || defined(I_AM_LINUX_HOST)) 00144 #define SDRAM1_BASE (CE2_BASE) + (SDRAM0_SZ) 00145 #elif (defined(I_AM_SLAVE_DSP)) 00146 #define SDRAM1_BASE (CE3_BASE) 00147 #endif 00148 #endif 00149 00150 /* The master DSP has a boot ROM at CE1; slaves each have a router FIFO */ 00151 #ifndef TI_EVM 00152 #if (defined(I_AM_MASTER_DSP) || defined(I_AM_NT_HOST) || defined(I_AM_LINUX_HOST)) 00153 #define BOOT_ROM_BASE (CE1_BASE) 00154 #define BOOT_ROM_SZ (0x80000) /* boot ROM is 512K */ 00155 #elif (defined(I_AM_SLAVE_DSP)) 00156 #define ROUTER_FIFO_BASE (CE1_BASE) 00157 #define ROUTER_FIFO_SZ (0x1000) /* 1K words */ 00158 #endif 00159 #endif 00160 00161 /************************************************************************************ 00162 * IDRAM items 00163 ************************************************************************************ 00164 * IDREGS_SZ bytes of IDRAM are reserved for communications registers. 00165 * IDATA_SZ bytes are reserved for important variables for which it's desirable they 00166 * be kept (for monitoring) in a fixed location. Note that this method has a 00167 * minor drawback in that the variables become 'far' data objects, they cannot be 00168 * declared 'external' and thus cannot be directly accessed by functions from files 00169 * other than the one that they were declared in; they must be accessed through 00170 * function calls to functions residing in the same file. See accessRegister.c and 00171 * eventHandler.c for examples. 00172 * IDRAM_MEM_SZ bytes are reserved for the linker to place general heap, stack and 00173 * 'near' data objects (arrays and structures which are not declared 00174 * 'far'). This memory corresponds to the IDRAM memory segment in the .cdb file. In 00175 * the slaves it also holds initialization data for variable values and constants. 00176 * 00177 * BURST_SZ bytes of IDRAM are reserved for the program to store data for immediate 00178 * use. On the slaves it might be a temporary store for data retrieved from 00179 * the router FPGA via DMA. This data might be quickly checked for errors and dumped 00180 * if none are found or analysed if errors are found. Or the data might be processed 00181 * and added to histograms being accumulated in the SDRAM. On the master it might be 00182 * a temporary store for data being transmitted to the front end electronics. 00183 * 00184 * **** THESE SIZES MUST BE THE SAME AS THE CORRESPONDING LENGTH PARAMETER OF MEMORY 00185 * SECTION MANAGER IN THE CONFIGURATION DATABASE FILE **** 00186 * 00187 * NOTE: If the memory section sizes are mistaken, the error will sometimes be caught 00188 * by the compiler at compile time. Another check is done at run time inside 00189 * checkMemBounds.c. Most larger data objects like the primitive buffers, text 00190 * buffers, and external burst buffers do not have variables and memory segments 00191 * declared for them; for these the space is 'virtually' allocated here and checked 00192 * in chekMemBounds.c 00193 * 00194 */ 00195 #define IDREGS_SZ (0x0060) 00196 #define IDATA_SZ (0x0800) 00197 #define IDRAM_MEM_SZ (0x77a0) 00198 #define BURST_SZ (0x8000) 00199 00200 #define IDRAM_ALLOCATED ((IDREGS_SZ)+(IDATA_SZ)+(IDRAM_MEM_SZ)+(BURST_SZ)) 00201 00202 #define IDREGS_BASE (IDRAM_BASE) 00203 #define IDATA_BASE ((IDREGS_BASE) + (IDREGS_SZ)) 00204 #define IDRAM_MEM_BASE ((IDATA_BASE) + (IDATA_SZ)) /* IDRAM_BASE is kept for the 00205 physical memory base */ 00206 #define BURST_BFR_BASE ((IDRAM_MEM_BASE) + (IDRAM_MEM_SZ)) 00207 00208 /* communication registers: used for the handshake for host to DSP primitive lists */ 00209 /* 0x00 */ 00210 #define STATUS_REG_0 (IDRAM_BASE) 00211 #define STATUS_REG_1 ((STATUS_REG_0) + sizeof(UINT32)) 00212 #define STATUS_REG_2 ((STATUS_REG_1) + sizeof(UINT32)) 00213 #define COMMAND_REG_0 ((STATUS_REG_2) + sizeof(UINT32)) 00214 00215 /* 0x10 */ 00216 #define DIAGNOSTIC_REG ((COMMAND_REG_0) + sizeof(UINT32)) 00217 #define TRAPSTAT_REG_0 ((DIAGNOSTIC_REG) + sizeof(UINT32)) 00218 #define TRAPSTAT_REG_1 ((TRAPSTAT_REG_0) + sizeof(UINT32)) 00219 #define LOOP_REG ((TRAPSTAT_REG_1) + sizeof(UINT32)) 00220 00221 /* 0x20 */ 00222 #define HCMD_STAT_REG_0 ((LOOP_REG) + sizeof(UINT32)) 00223 #define HCMD_STAT_REG_1 ((HCMD_STAT_REG_0) + sizeof(UINT32)) 00224 #define HSTAT_REG_0 ((HCMD_STAT_REG_1) + sizeof(UINT32)) 00225 #define HSTAT_REG_1 ((HSTAT_REG_0) + sizeof(UINT32)) 00226 00227 /* 0x30 */ 00228 #define RESERVED_REG_0 ((HSTAT_REG_1) + sizeof(UINT32)) 00229 #define RESERVED_REG_1 ((RESERVED_REG_0) + sizeof(UINT32)) 00230 #define RESERVED_REG_2 ((RESERVED_REG_1) + sizeof(UINT32)) 00231 #define RESERVED_REG_3 ((RESERVED_REG_2) + sizeof(UINT32)) 00232 00233 /* 0x40 */ 00234 #define RESERVED_REG_4 ((RESERVED_REG_3) + sizeof(UINT32)) 00235 #define RESERVED_REG_5 ((RESERVED_REG_4) + sizeof(UINT32)) 00236 #define RESERVED_REG_6 ((RESERVED_REG_5) + sizeof(UINT32)) 00237 #define RESERVED_REG_7 ((RESERVED_REG_6) + sizeof(UINT32)) 00238 00239 /* 0x50 */ 00240 #define HCMD_REG ((RESERVED_REG_7) + sizeof(UINT32)) 00241 #define TRAP_CMD_STAT ((HCMD_REG) + sizeof(UINT32)) 00242 00243 /* inter-dsp communication registers: used for the handshake between master and 00244 * slave DSPs when one sends a list for the other to process. These registers 00245 * reside in the IDRAM of each slave DSP. The addresses are known to both the 00246 * master and the slaves. Note that the write register for the slave is the read 00247 * register for the master and vice versa. 00248 * 00249 * These are NOT used in COMPACT mode, but they are still defined for the 00250 * alignment of the text, primitive and reply buffers. */ 00251 #if (defined(I_AM_MASTER_DSP) || defined(I_AM_NT_HOST) || defined(I_AM_LINUX_HOST)) 00252 #define INTR_DSP_HSHK_WR ((TRAP_CMD_STAT) + sizeof(UINT32)) 00253 #define INTR_DSP_HSHK_RD ((INTR_DSP_HSHK_WR) + sizeof(UINT32)) 00254 #elif defined(I_AM_SLAVE_DSP) 00255 #define INTR_DSP_HSHK_RD ((TRAP_CMD_STAT) + sizeof(UINT32)) 00256 #define INTR_DSP_HSHK_WR ((INTR_DSP_HSHK_RD) + sizeof(UINT32)) 00257 #endif 00258 00259 /************************************************************************************ 00260 * SDRAM0 items 00261 ************************************************************************************ 00262 *** THIS MUST BE THE SAME AS THE LENGTH PARAMETER OF MEMORY SECTION MANAGER:XPROG IN 00263 * THE CONFIGURATION DATABASE FILE **** 00264 */ 00265 #define XPROG_SZ (0x30000) 00266 00267 /* The ERR, INFO, DIAG and XFER buffers are the text buffers for sending messages 00268 * upstream to the host processor. Slave text buffers are communicated to the host 00269 * via the master XFER buffer. The XFER buffer is not used on the slaves. 00270 * The HOST_PRM and HOST_REP buffers are for primitive lists from the host and the 00271 * associated reply data. Host to slave primitive and associated reply data are 00272 * transferred via the master DSP. The inter-DSP transfer buffers are small buffers 00273 * used for sending simple primitive lists from DSP to DSP (master to slave and 00274 * vice-versa). Note that in COMPACT mode the buffers are actually in IDRAM. */ 00275 00276 #ifdef COMPACT 00277 #define TXT_BFR_SZ (0x800) 00278 #define INTR_DSP_PRM_BFR_SZ (0x800) 00279 #define INTR_DSP_REP_BFR_SZ (0x800) 00280 00281 #if (defined(I_AM_MASTER_DSP) || defined(I_AM_NT_HOST) || defined(I_AM_LINUX_HOST)) 00282 #define MDSP_PRM_BFR_SZ (0x2000) 00283 #define MDSP_REP_BFR_SZ (0x2000) 00284 #endif 00285 #define SDSP_PRM_BFR_SZ (0x2000) 00286 #define SDSP_REP_BFR_SZ (0x2000) 00287 00288 #define ERR_BFR_BASE (BURST_BFR_BASE) 00289 #define INFO_BFR_BASE ((ERR_BFR_BASE) + (TXT_BFR_SZ)) 00290 #define DIAG_BFR_BASE ((INFO_BFR_BASE) + (TXT_BFR_SZ)) 00291 #define XFER_BFR_BASE ((DIAG_BFR_BASE) + (TXT_BFR_SZ)) 00292 00293 #define INTR_DSP_PRM_BFR_BASE_SND ((XFER_BFR_BASE) +(TXT_BFR_SZ)) 00294 #define INTR_DSP_REP_BFR_BASE_SND ((INTR_DSP_PRM_BFR_BASE_SND)+(INTR_DSP_PRM_BFR_SZ)) 00295 #define INTR_DSP_PRM_BFR_BASE_PRC ((INTR_DSP_REP_BFR_BASE_SND)+(INTR_DSP_REP_BFR_SZ)) 00296 #define INTR_DSP_REP_BFR_BASE_PRC ((INTR_DSP_PRM_BFR_BASE_PRC)+(INTR_DSP_PRM_BFR_SZ)) 00297 00298 #if (defined(I_AM_MASTER_DSP) || defined(I_AM_NT_HOST) || defined(I_AM_LINUX_HOST)) 00299 #define MDSP_PRM_BFR_BASE ((INTR_DSP_REP_BFR_BASE_PRC) + (INTR_DSP_PRM_BFR_SZ)) 00300 #define MDSP_REP_BFR_BASE ((MDSP_PRM_BFR_BASE) + (MDSP_PRM_BFR_SZ)) 00301 #endif 00302 #define SDSP_PRM_BFR_BASE ((INTR_DSP_REP_BFR_BASE_PRC) + (INTR_DSP_PRM_BFR_SZ)) 00303 #define SDSP_REP_BFR_BASE ((SDSP_PRM_BFR_BASE) + (SDSP_PRM_BFR_SZ)) 00304 00305 #define XBURST_BFR_BASE ((SDRAM0_BASE) + (XPROG_SZ)) 00306 #define XBURST_BFR_SZ (0x38000) 00307 00308 #define BURST_BFR_RESERVED_BASE ((XBURST_BFR_BASE) +(XBURST_BFR_SZ)) 00309 #define BURST_BFR_RESERVED_SZ (0x8000) 00310 00311 #define HISTOGRAM_DEFAULT_BASE ((BURST_BFR_RESERVED_BASE) +(BURST_BFR_RESERVED_SZ)) 00312 #define SDRAM0_ALLOCATED ((HISTOGRAM_DEFAULT_BASE) -(SDRAM0_BASE)) 00313 00314 #else 00315 00316 #define TXT_BFR_SZ (0x8000) 00317 #define INTR_DSP_PRM_BFR_SZ (0x800) 00318 #define INTR_DSP_REP_BFR_SZ (0x800) 00319 00320 /* WARNING: In non-COMPACT compilations, the master & slave DSPs now have 00321 different size primitive & reply buffers. To accomodate this those 00322 buffers have different compilation constants defined. it also means that THE 00323 DSP_(PRM/REP)_BFR_BASE DEFINITIONS MUST BE THE LAST DEFINITIONS WHICH ARE 00324 COMMON TO BOTH DSP TYPES. THE TEXT BUFFERS AND INTER-DSP PRIM BUFFERS MUST 00325 BE DEFINED BEFORE THEM. */ 00326 #if (defined(I_AM_MASTER_DSP) || defined(I_AM_NT_HOST) || defined(I_AM_LINUX_HOST)) 00327 #define MDSP_PRM_BFR_SZ (0x40000) 00328 #define MDSP_REP_BFR_SZ (0x40000) 00329 #endif 00330 #define SDSP_PRM_BFR_SZ (0x20000) 00331 #define SDSP_REP_BFR_SZ (0x20000) 00332 00333 #define ERR_BFR_BASE ((SDRAM0_BASE) + (XPROG_SZ)) 00334 #define INFO_BFR_BASE ((ERR_BFR_BASE) + (TXT_BFR_SZ)) 00335 #define DIAG_BFR_BASE ((INFO_BFR_BASE) + (TXT_BFR_SZ)) 00336 #define XFER_BFR_BASE ((DIAG_BFR_BASE) + (TXT_BFR_SZ)) 00337 00338 #define INTR_DSP_PRM_BFR_BASE_SND ((XFER_BFR_BASE) +(TXT_BFR_SZ)) 00339 #define INTR_DSP_REP_BFR_BASE_SND ((INTR_DSP_PRM_BFR_BASE_SND)+(INTR_DSP_PRM_BFR_SZ)) 00340 #define INTR_DSP_PRM_BFR_BASE_PRC ((INTR_DSP_REP_BFR_BASE_SND)+(INTR_DSP_REP_BFR_SZ)) 00341 #define INTR_DSP_REP_BFR_BASE_PRC ((INTR_DSP_PRM_BFR_BASE_PRC)+(INTR_DSP_PRM_BFR_SZ)) 00342 00343 #if (defined(I_AM_MASTER_DSP) || defined(I_AM_NT_HOST) || defined(I_AM_LINUX_HOST)) 00344 #define MDSP_PRM_BFR_BASE ((INTR_DSP_REP_BFR_BASE_PRC) + (INTR_DSP_PRM_BFR_SZ)) 00345 #define MDSP_REP_BFR_BASE ((MDSP_PRM_BFR_BASE) + (MDSP_PRM_BFR_SZ)) 00346 #define XPROG2 ((MDSP_REP_BFR_BASE) + (MDSP_REP_BFR_SZ)) 00347 00348 #endif 00349 #define SDSP_PRM_BFR_BASE ((INTR_DSP_REP_BFR_BASE_PRC) + (INTR_DSP_PRM_BFR_SZ)) 00350 #define SDSP_REP_BFR_BASE ((SDSP_PRM_BFR_BASE) + (SDSP_PRM_BFR_SZ)) 00351 00352 #define XBURST_BFR_BASE ((SDSP_REP_BFR_BASE)+(SDSP_REP_BFR_SZ)) 00353 #define XBURST_BFR_SZ (0x38000) 00354 00355 #define BURST_BFR_RESERVED_BASE ((XBURST_BFR_BASE) +(XBURST_BFR_SZ)) 00356 #define BURST_BFR_RESERVED_SZ (0x8000) 00357 00358 #define HISTOGRAM_DEFAULT_BASE ((BURST_BFR_RESERVED_BASE) +(BURST_BFR_RESERVED_SZ)) 00359 #define SDRAM0_ALLOCATED ((HISTOGRAM_DEFAULT_BASE) -(SDRAM0_BASE)) 00360 00361 #endif 00362 00363 /* default position for trapped events is in high memory: whereas the burst buffers 00364 are always needed for trapping events, this is potentially reserved memory for 00365 gathering trapped events; it is intended to be a suggestion when running the event 00366 trapping task. */ 00367 #if (defined(I_AM_MASTER_DSP) || defined(I_AM_NT_HOST) || defined(I_AM_LINUX_HOST)) 00368 #define SLV_SDRAM1_BASE (0x03000000) 00369 #define SLV_SDRAM1_SZ (0x01000000) /* needed by VME host */ 00370 #define EVENT_TRAP_DEFAULT_SZ (0x20000) 00371 #define EVENT_TRAP_DEFAULT_BASE ((SLV_SDRAM1_BASE) +(SLV_SDRAM1_SZ) \ 00372 -(EVENT_TRAP_DEFAULT_SZ)) 00373 #else 00374 #define EVENT_TRAP_DEFAULT_SZ (0x20000) 00375 #define EVENT_TRAP_DEFAULT_BASE ((SDRAM1_BASE) +(SDRAM1_SZ) \ 00376 -(EVENT_TRAP_DEFAULT_SZ)) 00377 #endif 00378 00379 /* SDRAM1: free space for application defined data */ 00380 #if (defined(I_AM_MASTER_DSP) || defined(I_AM_NT_HOST) || defined(I_AM_LINUX_HOST)) 00381 #define MODULE_DATA_BASE SDRAM1_BASE 00382 #define MODULE_DATA_SZ 0x00080000 /* .5 MB */ 00383 00384 #define SDRAM1_FREE_BASE ((MODULE_DATA_BASE) +(MODULE_DATA_SZ)) 00385 00386 /* if running on the TI evaluation module, the 6701 DSP communication buffers 00387 must be offset & 6701 replies faked. The 6701s are put right before SDRAM1 */ 00388 #define EVM_SLV_REG_BASE(slv) (SDRAM1_BASE - 0x2000 + 0x80*(slv)) 00389 #define EVM_RRIF_REG_BASE ((SDRAM1_BASE) - 0x1000) 00390 00391 #else 00392 #define SDRAM1_FREE_BASE (SDRAM1_BASE) 00393 #endif 00394 00395 #define SDRAM1_ALLOCATED ((SDRAM1_FREE_BASE) -(SDRAM1_BASE)) 00396 00397 #if defined(TI_EVM) /* need a histogram base for SDRAM1 */ 00398 #define HISTOGRAM_BASE1 ((SDRAM1_BASE) +(0x40000)) 00399 #endif 00400 00401 /************************************************************************************ 00402 * RRIF memory mapped items - CE0 on ROD; EVM_RRIF_REG_BASE on TI_EVM (no RRIF) 00403 ************************************************************************************/ 00404 #ifdef I_AM_MASTER_DSP 00405 /* base address for memory mapped registers and FIFOs */ 00406 00407 #ifdef TI_EVM 00408 #define REG_BASE (EVM_RRIF_REG_BASE) 00409 #else 00410 #define REG_BASE (CE0_BASE) 00411 #endif 00412 00413 /* offsets into each device These are RRIF-centric offsets, i.e. from the DSP 00414 * point of view they need to be left shifted 2 bits. This is done where needed 00415 * in the files containing the access routines. */ 00416 #define FMT_BASE (0x0) 00417 #define EFB_BASE (0x800) 00418 #define RTR_BASE (0x900) 00419 #define RRIF_BASE (0x1000) 00420 #define FIFO_BASE (0x1800) 00421 #define BOC_BASE (0x2000) 00422 #define SLV_BASE (0xE0000) 00423 00424 #define LED_OFFSET 0x100 00425 #define HEARTBEAT_ADR ((UINT32 *)(((RRIF_BASE + LED_OFFSET) << 2) + REG_BASE)) 00426 00427 #endif 00428 00429 #ifdef I_AM_SLAVE_DSP 00430 #define ROUTER_FIFO_ADDR (CE1_BASE) 00431 #endif 00432 00433 #endif