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comRegDfns.h

00001 /************************************************************************************
00002  *
00003  * comRegDfns.h:  Defines bits in the registers of the RRIF dual port register block
00004  *               and the master-slave communication mailbox (in each slave IDRAM).
00005  *
00006  *  Damon Fasching, UW Madison (510)486-5230               fasching@wisconsin.cern.ch
00007  *
00008  *  modifications/bugs    
00009  *   - Reserved bits in the command register for slave IDs            05.05.02 dpsf
00010  ************************************************************************************/
00011 #ifndef COM_REG_DFNS
00012 #define COM_REG_DFNS
00013 
00014 #include "smSendTxtBuff.h"         /* pick up N_TXT_BUFFS */
00015 // #include "rodConfiguration.h"      /* pick up N_SLV_DSPS */
00016 #define N_SLV_DSPS 4
00017 
00018 /* STATUS_REG_0 */
00019 #define SR_RUNNING                0
00020 #define SR_BUSY                   (1 + (SR_RUNNING))
00021 #define SR_EXECUTING              (1 + (SR_BUSY))
00022 #define SR_PAUSED                 (1 + (SR_EXECUTING))
00023 
00024 #define SR_OUT_LIST_RDY           (1 + (SR_PAUSED))
00025 #define SR_DSP_ACK                (1 + (SR_OUT_LIST_RDY))
00026 
00027 #define SR_DMA_ACCESS_ACK         (1 + (SR_DSP_ACK))
00028 #define SR_DMA_ACCESS_ERR         (1 + (SR_DMA_ACCESS_ACK))
00029 
00030 #define SR_TXT_BUFF_NE(x)         (1 + (x) + (SR_DMA_ACCESS_ERR))
00031 /* the next available register bit is (1 + (N_TXT_BUFFS) + (SR_DMA_ACCESS_ERR)) */
00032 
00033 #define SR_TXT_BUFF_PROC(x)       (1 + (x) + (SR_TXT_BUFF_NE(N_TXT_BUFFS-1)))
00034 
00035 #define SR_NTASKS                 (1 + (SR_TXT_BUFF_PROC(N_TXT_BUFFS-1)))
00036 #define SR_NTASKS_W               3
00037 #define SR_EVM                    (3 + (SR_NTASKS))          /* Slave DSPs */
00038 #define SR_IDLS_ACTIVE            (1 + (SR_EVM))             
00039 #define SR_IDLP_ACTIVE            (1 + (SR_IDLS_ACTIVE))     /* Master DSP */
00040 
00041 /* STATUS_REG_1 */
00042 #define SR_PRIM_LIST_INDEX      0
00043 #define SR_PRIM_LIST_INDEX_W    4
00044 #define SR_PRIM_INDEX          ((SR_PRIM_LIST_INDEX) + (SR_PRIM_LIST_INDEX_W))
00045 #define SR_PRIM_INDEX_W        20
00046 
00047 /* STATUS_REG_2 */
00048 #define SR_SLVCOMM(x)             (x)
00049 #define SR_HLTS(x)                (1 + (x) +(SR_SLVCOMM(N_SLV_DSPS-1)))
00050 
00051 
00052 /* COMMAND_REG_0 */
00053 #define CR_IN_LIST_RDY            0
00054 #define CR_PAUSE                  (1 + (CR_IN_LIST_RDY))
00055 #define CR_RESUME                 (1 + (CR_PAUSE))
00056 #define CR_ABORT                  (1 + (CR_RESUME))
00057 #define CR_TXT_BUFF_RR(x)         (1 + (x) + (CR_ABORT))
00058 /* the next available register bit is (1 + (N_TXT_BUFFS) + (CR_ABORT))  */
00059 #define CR_ID                     (1 + CR_TXT_BUFF_RR(N_TXT_BUFFS-1))
00060 #define CR_ID_W                   2   /* IDs for slave DSPs- on master, unused. */
00061 #define CR_DMA_ACCESS_REQ         ((CR_ID_W) + (CR_ID))
00062 #define CR_FLUSH_EVENTS           (1 + (CR_DMA_ACCESS_REQ))   /* Slave DSPs */
00063 #define CR_IDLP_ACTIVE            (1 + (CR_FLUSH_EVENTS))     /* Slave DSPs */
00064 
00065 /* Expert Register */
00066 #define ER_DISP_ROD_REG_ID       0
00067 #define ER_DISP_SERIAL_LOOPS     1
00068 #define ER_DISP_LINK_DATA        2
00069 #define ER_HISTO_1               3
00070 #define ER_DISP_MIRROR_CTIME     4
00071 #define ER_HCTRL_CAPTURE_SET     5
00072 #define ER_STEP_CTRL             6
00073 #define ER_STEP_TRIGGER          7
00074 #define ER_DELAY                 8
00075 #define ER_SOFT_BC_RESET         9
00076 #define ER_MUTE                  10
00077 #define ER_ARDY                  11
00078 #define ER_MAINLOOP_TOGGLE       12
00079 #define ER_ROUTINE_ENTER         13
00080 #define ER_MAINLOOP_DELAYLOOPS   14
00081 #define ER_TIMING_DISPLAY        15
00082 #define ER_DMA_ACK               16
00083 #define ER_SLAVE_WRITE_TEST      17
00084 #define ER_ISR_DELAY             18
00085 
00086 
00087 /* Histogram Command & Status Registers */
00088 #if    (defined(I_AM_LINUX_HOST)||defined(I_AM_MASTER_DSP))
00089     #define HCMD_BINEVT     0
00090     #define HCMD_BINEVT_W   12
00091     #define HCMD_SET        12
00092     #define HCMD_SET_W      4
00093     #define HCMD_BIN        16
00094     #define HCMD_BIN_W      16
00095 
00096     #define HSR0_SLV0        0
00097     #define HSR0_SLV1        8
00098     #define HSR0_SLV2        16
00099     #define HSR0_SLV3        24
00100     #define HSR0_SLV_W       8
00101     
00102 #endif
00103 
00104 /* Definitions of the slave's command and status registers are different; 
00105    master must know both. */
00106 #define HCMD_SLV_BINEVTS    0
00107 #define HCMD_SLV_BINEVTS_W  12
00108 #define HCMD_SLV_SET        12
00109 #define HCMD_SLV_SET_W      4
00110 #define HCMD_SLV_BIN        16
00111 #define HCMD_SLV_BIN_W      16
00112 
00113 #define HSR0_SLV_RDY    0
00114 #define HSR0_SLV_EXP    1
00115 #define HSR0_SLV_PROC   2
00116 #define HSR0_SLV_DONE   3
00117 
00118 #define HSR0_SLV_EVTS_REC    8
00119 #define HSR0_SLV_EVTS_REC_W  12
00120 #define HSR0_SLV_SET         20
00121 #define HSR0_SLV_SET_W       4
00122 #define HSR0_SLV_BIN         24
00123 #define HSR0_SLV_BIN_W       8
00124 
00125 #define HSR1_SLV_EVT_LEN       0
00126 #define HSR1_SLV_EVT_LEN_W    16
00127 #define HSR1_SLV_EVT_PTIME    16
00128 #define HSR1_SLV_EVT_PTIME_W  16
00129 
00130 
00131 /* Trap status register 0 */
00132 #define TSR0_TRANSMIT          0
00133 #define TSR0_TRAILER           1
00134 #define TSR0_HEADER            2
00135 
00136 #define TSR0_ERROR             4
00137 #define TSR0_HEADER_ERROR      5
00138 #define TSR0_TRAILER_ERROR     6
00139 #define TSR0_DATA_ERROR        7
00140 
00141 #define TSR0_EVT_FRAME_CNT     8
00142 #define TSR0_EVT_FRAME_CNT_W   8
00143 
00144 #define TSR0_IFRAME_CNT        16
00145 #define TSR0_IFRAME_CNT_W      8
00146 #define TSR0_XFRAME_CNT        24
00147 #define TSR0_XFRAME_CNT_W      8
00148 
00149 /* Trap status register 1 */
00150 #define TSR1_EVT_TOTAL_PROC_TIME       0
00151 #define TSR1_EVT_TOTAL_PROC_TIME_W     16
00152 #define TSR1_IFRAME_RELEASE_CNT        16
00153 #define TSR1_IFRAME_RELEASE_CNT_W      8
00154 #define TSR1_XFRAME_RELEASE_CNT        24
00155 #define TSR1_XFRAME_RELEASE_CNT_W      8
00156 
00157 
00158 
00159 /* The loop register (increments once per loop */
00160 #define LR_CNT                0
00161 #define LR_CNT_W             32
00162 
00163 
00164 /* INTR_DSP_HSHK_WR and INTR_DSP_HSHK_RD */
00165 /* The following bits are defined in each of these registers.  They are used for the
00166  * handshake between the master and a slave when either sends a list to the other.
00167  * The state machine is simpler than for host-originated lists, e.g. there is no
00168  * option to pause. */
00169  
00170 #define INTR_DSP_IN_LIST_RDY    (0)
00171 #define INTR_DSP_ABORT          ((INTR_DSP_IN_LIST_RDY) + 1)
00172 #define INTR_DSP_ACK            ((INTR_DSP_ABORT) + 1)
00173 #define INTR_DSP_OUT_LIST_RDY   ((INTR_DSP_ACK) + 1)
00174 
00175 #endif
00176 

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