Connections to the Bias Card
*** NOTE changed HV connections to JP1 ***
Front panel connections are (from the top):
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Number Type Function
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SK1 Lemo size 00 coax Power Interlock Input : NIM level
JP3 20 way "IDC" header Connections to SLL card
SK2 Lemo size 0S 2 way Det. HV "A" input
SK3 Lemo size 0S 2 way Det. HV "B" input
SK4 Lemo size 1S 4 way Det. HV o/p to detector module
JP1 50 way "IDC" header Connections to detector module
SK5 Lemo size 1B 4 way Vcc and Vdd feeds to det module
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Notes:
1. "S" series multiway Lemos have mix of pins and sockets
2. "B" series multiway pcb-mounting Lemo connectors are 100% sockets
3. The 2 HV inputs are routed via the Farside HV monitoring daughter
card to the Lemo HV output, SK4.
These connections may optionally be routed to the 50 way JP1 via
jumpers.
SK2 connections: 2 pin Lemo 0S Front View
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Pin Net Function Notes |---\
1 VDET_AC HV "A" Common Near ground |* o |
2 VDET_AI HV "A" Input +ve / -ve |___/
----------------------------------------------------- 2 1 ----
SK3 connections: 2 pin Lemo 0S Front View
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Pin Net Function Notes |---\
1 VDET_BC HV "B" Common Near ground |* o |
2 VDET_BI HV "B" Input +ve / -ve |___/
----------------------------------------------------- 2 1 ----
SK4 connections: 4 pin Lemo 1S Front View
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Pin Net Function Notes |-----\
1 VDET_BF HV "B" Feed 3 | * o | 2
2 VDET_AF HV "A" Feed 4 | * o | 1
3 VDET_AC HV "A" Common |_____/
4 VDET_BC HV "B" Common |
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SK5 connections: 4 pin Lemo 1B Front View
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Pin Net Function |-----\
1 AGND Analogue Ground - return for Icc 2 | o o | 1
2 MOD_VCC Vcc feed to detector module 3 | o o | 4
3 GND Digital Ground - return for Idd |_____/
4 MOD_VDD Vdd feed to detector module |
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JP1 connections: (pin1 = bottom, RHS)
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Pin Net Function Function
# Name default/if PECL card if LVDS card
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1 OUT0 BClk BClk0
2 OUT0_B & inverse & inverse
3 OUT2 P_CTCP CTL0
4 OUT2_B & inverse & inverse
5 OUT1 N_CTCP BClk1
6 OUT1_B & inverse & inverse
7 LI_0 Data stream 0 to SLL ditto
8 ~LI_0 & inverse ditto
9 LI_1 Data stream 1 to SLL ditto
10 ~LI_1 & inverse ditto
11 VDDSEN Vdd Sense wire ditto
12 DGNDSEN Dig'l Ground Sense wire ditto
13 VREFCDP Vref to CDP
14 M5V -5V for support card amp
15 CR4 CMOS CReg[4] ditto
16 AGND Analogue Ground
17 CR5 CMOS CReg[5] ditto
18 CR6 CMOS CReg[6] ditto
19 OUT3 No Conection CTL1
20 OUT3_B No Conection & inverse
21 CAL3P Cal3 signal ditto
22 CAL3N & inverse ditto
23 CAL2P etc
24 CAL2N
25 CAL1P etc
26 CAL1N
27 CAL0P etc
28 CAL0N
29 VCALHI for support card cal cct
30 VHISEN ditto
31 VCALLOW ditto
32 VLOWSEN ditto
33 V7 7 volt feed
34 VI1 CAFE preamp current
35 VCCSEN Vcc sense wire
36 AGNDSEN Analogue Ground sense wire
37 ATTCALP Cal Volts for ATT, +ve
38 ATTCALN Cal Volts for ATT, -ve
39 PVTHI P side threshold hi (Note A)
40 PVTLOW P side threshold low
41 NVTHI N side threshold hi (Note A)
42 NVTLOW N side threshold low
was 43 VDET_AFS Det HV "A" Feed Switched
was 44 VDET_ACS Det HV "A" Common Switched
was 45 VDET_BFS Det HV "B" Feed Switched
was 46 VDET_BCS Det HV "B" Common Switched
43 VDET_BCS Det HV "B" Common Switched
44 VDET_ACS Det HV "A" Common Switched
45 VDET_BFS Det HV "B" Feed Switched
46 VDET_AFS Det HV "A" Feed Switched
47 - Spare
48 - Spare
49 DAC8_F Programmable voltage
50 DAC8_R Reference for above
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Note A: these pins are connected to VccSenBuf on BC96 (exactly as
on original Bias Card).
Connections between SLL and BC96: (one SLL drives 2 BC96's)
--------------------------------- (special cable assembly used)
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DSP First BC96 Second BC96 Termination
SLL 34 way JP3 20 way JP3 20 way
Pins Signal Pins Signal Pins Signal
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1, 2 GS_0 - - - -
3, 4 LI_0 1, 2 LI0 - -
5, 6 LI_1 3, 4 LI1 - -
7, 8 LI_2 - - 1, 2 LI0
9,10 LI_3 - - 3, 4 LI1
11,12 No Conn - - - -
13,14 No Conn - - - -
15,16 BCK 5, 6 BCK 5, 6 BCK
17,18 FO_0 7, 8 FO_0 - -
19,20 FO_1 9,10 FO_1 - -
21,22 FO_2 - - 7, 8 FO_0
23,24 FO_3 - - 9,10 FO_1
25,26 FO_4 11,12 FO_4 11,12 FO_4
27,28 FO_5 13,14 FO_5 13,14 FO_5
29,30 FO_6 15,16 FO_6 15,16 FO_6
31,32 FO_7 17,18 FO_7 17,18 FO_7
33,34 GS_1 - - - -
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Note: For all signal pairs, even pin carries inverted signal
PECL Driver Card:
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JP1 (50 way) Expected Use Description
Pins Signal
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1, 2 OUT0 BClk Copy of BCK
3, 4 OUT2 P_CTC Copy of FO_0
5, 6 OUT1 N_CTC Copy of FO_1
19,20 OUT3 Not Driven No Connection
21,22 CAL3 CAL3 Copy of FO_7
23,24 CAL2 CAL2 Copy of FO_6
25,26 CAL1 CAL1 Copy of FO_5
27,28 CAL0 CAL0 Copy of FO_4
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LVDS Driver Card:
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JP1 (50 way) Expected Use Description
Pins Signal
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1, 2 OUT0 BClk0 Copy of BCK gated by CR[0]
3, 4 OUT2 CTL0 Copy of FO_0 gated by CR[2]
5, 6 OUT1 BClk1 Copy of BCK gated by CR[1]
19,20 OUT3 CTL1 Copy of FO_0 gated by CR[3]
21,22 CAL3 CAL3 Copy of FO_7
23,24 CAL2 CAL2 Copy of FO_6
25,26 CAL1 CAL1 Copy of FO_5
27,28 CAL0 CAL0 Copy of FO_4
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Notes:
1. CR[6:0] are the 7 bits written to the BC96 Control Register
2. The gating of the OUT signals is to allow the Clock and Control
redundancy schemes to be tested.
3. The provision of CR[4,5,6] on JP1 is also needed for this purpose.
4. It is invisaged that FO_0 would be driven from the SLL with
either combined Trigger and Control, or combined Clock, Trigger
and Control, as required.
John Hill Last update 15 July 1997