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00025 typedef struct {
00026 UINT32 status[2];
00027 #if defined(I_AM_HOST)
00028 UINT32 unused;
00029 #else
00030 UINT32 status2;
00031 #endif
00032 UINT32 command;
00033
00034 UINT32 diagnostic;
00035 UINT32 trapStat[3];
00036
00037 UINT32 hStat[2];
00038 UINT32 hSdspStat[4];
00039
00040 UINT32 listStatus;
00041 UINT32 trapReq;
00042
00043 UINT32 time;
00044 UINT32 loop;
00045 UINT32 memoryMap;
00046 UINT32 taskState;
00047
00048 UINT32 hCmd;
00049 UINT32 trapCmd;
00050
00051 UINT32 reservedReg[7];
00052 UINT32 listCnt;
00053
00054
00055
00056
00057
00058
00059 #if (defined(I_AM_HOST))
00060 UINT32 privateDsp[2];
00061 #elif (defined(I_AM_MASTER_DSP))
00062 UINT32 interDspHshkWr, interDspHshkRd;
00063 #elif (defined(I_AM_SLAVE_DSP))
00064 UINT32 interDspHshkRd, interDspHshkWr;
00065 #endif
00066
00067 } CommRegs;
00068
00069
00070
00071 #define STATUS_REG_0 (IDREGS_BASE)
00072 #define STATUS_REG_1 ((STATUS_REG_0) + 4)
00073 #define STATUS_REG_2 ((STATUS_REG_1) + 4)
00074 #define COMMAND_REG_0 ((STATUS_REG_2) + 4)
00075
00076 #define LIST_CNT_REG (STATUS_REG_1)
00077
00078
00079 #define DIAGNOSTIC_REG ((COMMAND_REG_0) + 4)
00080 #define TRAPSTAT_REG1_0 ((DIAGNOSTIC_REG) + 4)
00081 #define TRAPSTAT_REG1_1 ((TRAPSTAT_REG1_0) + 4)
00082 #define TRAPSTAT_REG1_2 ((TRAPSTAT_REG1_1) + 4)
00083
00084
00085 #define HSTATUS_REG_0 ((TRAPSTAT_REG1_2) + 4)
00086 #define HSTATUS_REG_1 ((HSTATUS_REG_0) + 4)
00087 #define HSSTAT_REG_0 ((HSTATUS_REG_1) + 4)
00088 #define HSSTAT_REG_1 ((HSSTAT_REG_0) + 4)
00089
00090
00091 #define HSSTAT_REG_2 ((HSSTAT_REG_1) + 4)
00092 #define HSSTAT_REG_3 ((HSSTAT_REG_2) + 4)
00093 #define LIST_STATUS_REG ((HSSTAT_REG_3) + 4)
00094 #define TRAP_REQ_REG ((LIST_STATUS_REG) + 4)
00095
00096
00097 #if ((defined(I_AM_MASTER_DSP)) || (defined(I_AM_HOST)))
00098 #define SDSP_HSTATUS_REG_0 (HSSTAT_REG_0)
00099 #define SDSP_HSTATUS_REG_1 (HSSTAT_REG_1)
00100 #define SDSP_HSTATUS_REG_2 (HSSTAT_REG_2)
00101 #define SDSP_HSTATUS_REG_3 (HSSTAT_REG_3)
00102 #endif
00103
00104
00105 #define TIME_REG ((TRAP_REQ_REG) + 4)
00106 #define LOOP_REG ((TIME_REG) + 4)
00107 #define MEMORY_MAP_REG ((LOOP_REG) + 4)
00108 #define TASK_STATE_REG ((MEMORY_MAP_REG) + 4)
00109
00110
00111 #define HCMD_REG ((TASK_STATE_REG) + 4)
00112 #define TRAP_CMD_REG1 ((HCMD_REG) + 4)
00113 #define RESERVED_REG_0 ((TRAP_CMD_REG1) + 4)
00114 #define RESERVED_REG_1 ((RESERVED_REG_0) + 4)
00115
00116
00117 #define TRAP_CMD_STAT1 (TRAP_CMD_REG1)
00118 #define HCMD_STAT_REG_0 (HSTATUS_REG_0)
00119 #define HCMD_STAT_REG_1 (HSTATUS_REG_1)
00120 #if (defined(I_AM_SLAVE_DSP))
00121 #define HSTAT_REG_0 (HSSTAT_REG_0)
00122 #define HSTAT_REG_1 (HSSTAT_REG_1)
00123 #define HSTAT_REG_2 (HSSTAT_REG_2)
00124 #define HSTAT_REG_3 (HSSTAT_REG_3)
00125 #endif
00126
00127
00128 #define RESERVED_REG_2 ((RESERVED_REG_1) + 4)
00129 #define RESERVED_REG_3 ((RESERVED_REG_2) + 4)
00130 #define RESERVED_REG_4 ((RESERVED_REG_3) + 4)
00131 #define RESERVED_REG_5 ((RESERVED_REG_4) + 4)
00132
00133
00134 #define RESERVED_REG_6 ((RESERVED_REG_5) + 4)
00135 #define RESERVED_REG_7 ((RESERVED_REG_6) + 4)
00136
00137
00138 #if defined(I_AM_HOST)
00139 #define PRIVATE_DSP_0 ((RESERVED_REG_7) + 4)
00140 #define PRIVATE_DSP_1 ((PRIVATE_DSP_0) + 4)
00141 #elif defined(I_AM_MASTER_DSP)
00142 #define INTR_DSP_HSHK_WR ((RESERVED_REG_7) + 4)
00143 #define INTR_DSP_HSHK_RD ((INTR_DSP_HSHK_WR) + 4)
00144 #elif defined(I_AM_SLAVE_DSP)
00145 #define INTR_DSP_HSHK_RD ((RESERVED_REG_7) + 4)
00146 #define INTR_DSP_HSHK_WR ((INTR_DSP_HSHK_RD) + 4)
00147 #endif