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rodConfiguration.h

00001 /************************************************************************************
00002  * rodConfiguration.h
00003  *
00004  *  synopsis: Describes ROD specific hardware details, e.g. is this an SCT or a pixel
00005  *           ROD, how many formatter FPGAs are there...
00006  *
00007  *  Damon Fasching, UW Madison                            fasching@wisconsin.cern.ch
00008  *  Douglas Ferguson, UW Madison   (510) 486-5230         dpferguson@lbl.gov
00009  *
00010  *  modifications/bugs    
00011  *   - Moved rodConfiguration #defines here (were in primParams.h)   11.04.02 dpsf
00012  ************************************************************************************/
00013 #ifndef ROD_CONFIGURATION
00014 #define ROD_CONFIGURATION
00015 
00016 #include "processor.h"
00017 
00018 //Some dataflow parameters:
00019 #define EFBS_PER_ROD               2
00020 #define FORMATTERS_PER_EFB         4
00021 #define FORMATTERS_PER_ROD         (FORMATTERS_PER_EFB*EFBS_PER_ROD)
00022 #define LINKS_PER_FORMATTER        12
00023 #define DATA_LINKS_PER_EFB         (LINKS_PER_FORMATTER*FORMATTERS_PER_EFB)
00024 #define DATA_LINKS_PER_ROD         (DATA_LINKS_PER_EFB * EFBS_PER_ROD)
00025 #define CTRL_LINKS_PER_ROD         (DATA_LINKS_PER_ROD / 2)
00026 #define STROBE_DELAYS_PER_BOC      24
00027 #define INMEM_DEPTH                0x8000
00028 #define INMEM_DEPTH_REV_B          0x1000
00029 #define DEFAULT_CAPTURE_LINK       0x80
00030  
00031 //Number of SDSPs:
00032 #if (defined(I_AM_MASTER_DSP) || defined(I_AM_HOST))
00033   #define N_SDSP  4
00034 #endif
00035 #ifdef I_AM_SLAVE_DSP
00036   #define N_SDSP  1
00037 #endif
00038 
00039 /* 6713 phase lock loop registers & device config register; these are used by the MDSP
00040    while setting a Rev. E ROD's SDSP clocks. */
00041 #define PLL_TIMEOUT 5000000  // .5 sec.
00042 
00043 #define SDSP6713_PLLCSR    0x01b7c100
00044 #define SDSP6713_PLLM      0x01b7c110
00045 #define SDSP6713_PLLDIV0   0x01b7c114
00046 #define SDSP6713_DEVCFG    0x019c0200
00047 
00048 //Configuration data structures:
00049 struct SlvDspConfig {
00050     UINT8 present;
00051     UINT8 commOnOff;
00052     UINT8 type;
00053     UINT8 clkSpeed;
00054 };
00055 
00056 typedef struct RodConfig {
00057     UINT32 detector;
00058     UINT32 rodType;
00059     UINT32 boardClockInMHz;
00060     UINT32 DSPClockInMHz;
00061     UINT32 numSlaves;
00062     UINT32 numSlvsCommOn;
00063 
00064     /* The formatter modes reflect register settings on the formatter in question
00065        (one nibble per formatter), with different meanings for SCT & Pixel. For
00066        SCT 00= Off, 01= On in condensed mode, and 02= On in expanded format mode. 
00067        For Pixels, 00= Off, 01= On in 40 MHz mode, 02= 80 MHz mode, and 03= 160
00068        MHz mode: */
00069 
00070     UINT32  formatterMode;
00071     struct SlvDspConfig slvDspConfig[N_SDSP];
00072 } RodConfig;
00073 
00074 #if defined (SCT_ROD)
00075     #define RODCFG_FMT_OFF        0x0
00076     #define RODCFG_FMT_CONDENSED  0x1
00077     #define RODCFG_FMT_EXPANDED   0x2
00078 #elif defined(PIXEL_ROD)
00079     #define RODCFG_FMT_OFF        0x0
00080     #define RODCFG_FMT_40_MHZ     0x1
00081     #define RODCFG_FMT_80_MHZ     0x2
00082     #define RODCFG_FMT_160_MHZ    0x3
00083 #endif
00084 
00085 /* Some modes are additive; e.g. CALIBRATION +SIMULATION. The ROD will
00086    return an error for those modes which are incompatible. */
00087 
00088 /* NDT: Sets the data path according to the simulation type or link_data
00089         +capture,  sets the atlas running mode to true so that router is
00090         not allowed to apply back-pressure, and sets the link masks and
00091         assoc. variables according to the information stored in the 
00092         INIT module configuration set. Automatic inmem readout triggers an
00093         automatic readout of the inmems' link(s) into a MDSP buffer after
00094         completion of each serial stream output. */
00095 //"dummy" mode modifiers (=> exit cfg readback, evt capture, or simulation):  
00096 #define NOCAPTURE_MODE                    0
00097 #define NOSIMULATION_MODE                 0
00098 #define NORMAL_MODE                       0
00099 
00100 //mode modifiers:
00101 #define SIMULATION_MODE                   0x0001
00102 #define CONFIG_READBACK_MODE              0x0002
00103 #define INMEM_EVT_CAPTURE_MODE            0x0004
00104 #define INMEM_AUTO_READOUT_MODE           0x0008
00105 #define CALIBRATION_SLINK_OVERRIDE_MODE   0x0010
00106 #define TIM_TRIGGER_MODE                  0x0020
00107 
00108 //ROD modes:
00109 #define ROD_INIT_MODE            0x00010000 
00110 #define DATA_TAKING_MODE         0x00020000 
00111 #define CALIBRATION_MODE         0x00040000
00112 
00113 /* routine flags: */
00114 #define SET_MODE        0
00115 #define STORE_MODE      1
00116 #define RESTORE_MODE    2
00117 #define MODIFY_MODE     3
00118 
00119 typedef struct {
00120     UINT8  sim, cfgReadback, inmemEvtCapture, autoInmemReadout;
00121     UINT32 rodMode, unused[2];
00122     #if  (  defined(I_AM_MASTER_DSP) || defined(I_AM_HOST))
00123         UINT32 rcfCmd[2], rtrCmdStat,  evtsPerL1A;
00124         UINT32 lutSelect, unused1[3], cmdMask[2][2], fmtCfg[8];
00125         #ifdef PIXEL_ROD
00126         UINT32 fmt_evtsPerL1A[8];
00127         #endif
00128     #endif
00129 } RodModeCfg;
00130 
00131 #if  (defined(I_AM_MASTER_DSP) || defined(I_AM_HOST))
00132     /* Link masks defined bitwise: set all masks on= CL on +DLP +LCFG on. Note that
00133        settings within the same group are mutually exclusive; the values are set so
00134        that the mask setting routine will ignore inappropriate mixtures. */
00135 
00136     #define DATA_LINK_MASKED  0x1  /* Dynamic modebits setting for disabled link */
00137     #define DATA_LINK_PLAY    0x3  /* Normal dyn. modebits setting for enabled link */
00138     #define DATA_LINK_SKIP    0x7  /* Sets link so that it skips over the next event */ 
00139     #define DATA_LINK_D1P1    0xe  /* Link will dump 1st event, play out 2nd. */ 
00140 
00141     #define COMMAND_LINK_OFF 0x40   
00142     #define COMMAND_LINK_ON  0x60   
00143 
00144     #define LINK_CFG_OFF     0x100   /* Link off; for initialization of ROD. */
00145     #define LINK_CFG_ON      0x300   /* Link on;  for initialization of ROD. */
00146 
00147     /* Internal masks: */
00148     #define DATA_LINK      0x00f
00149     #define COMMAND_LINK   0x0f0
00150     #define LINK_CFG       0xf00
00151 
00152 
00153     //Storage flag settings for setLinkMasks:
00154     #define INIT_MASK             0
00155     #define SET_MASK              1
00156     #define UPDATE_MASK           2
00157     #define SWITCH_MASK           3
00158     #define STORE_MASK            4
00159     #define COMPUTE_MASK_DELTAS   5
00160 
00161     /* Link Modifications are specialized commands used in conjunction with the 
00162        SCT setChipVariable routine. They are converted internally to an UPDATE
00163        command & control the way the 2 data links are treated: */
00164     #ifdef SCT_ROD
00165         #define LINK_MOD_LOWER  6
00166         #define LINK_MOD_UPPER  7
00167         #define LINK_MOD_BOTH   8
00168     #endif
00169 
00170     typedef struct FmtMask {
00171         UINT16 fmtCfg[FORMATTERS_PER_ROD];
00172         UINT32 dataLinkMask[3], unused;
00173     } FmtMask;
00174 
00175     typedef struct DynMask {
00176         /*                                 MB0/1 */
00177         UINT16 modeBits[FORMATTERS_PER_ROD][2];
00178     } DynMask;
00179 
00180     typedef struct CmdMask {
00181         UINT32 highMask;
00182         UINT32 lowMask, unused[2];
00183     } CmdMask;
00184     
00185     typedef struct DeltaMask {
00186         UINT32 modeBits;
00187         UINT8  cmdLine, fmtCfg, dataLinkMask, unused;
00188     } DeltaMask;
00189 
00190     #define DELTA_SP0_LO  1
00191     #define DELTA_SP0_HI  2
00192     #define DELTA_SP1_LO  4
00193     #define DELTA_SP1_HI  8
00194 
00195     #define DELTA_DFLT_MB0(fmt)  (1<<(4*(fmt) +0))
00196     #define DELTA_DFLT_MB1(fmt)  (1<<(4*(fmt) +1))
00197     #define DELTA_CRTV_MB0(fmt)  (1<<(4*(fmt) +2))
00198     #define DELTA_CRTV_MB1(fmt)  (1<<(4*(fmt) +3))
00199 
00200     #define DELTA_FMT_CFG(fmt)        (1<<(fmt))
00201     #define DELTA_DATA_LINK_MASK(i)   (1<<(i))
00202 
00203 
00204     /* The following definition is for global updates affecting all modules which have
00205        been added to a mask set. Note that it cannot conflict with ALL_MODULES and
00206        NO_MODULE which are defined in primParams.h */
00207     #define ALL_SET_MODULES  0xf0
00208 
00209     /* The MaskConfigData structure  is used to set the command & data link masks
00210        when a new group of modules is being addressed. Up to 8 'mask sets' are
00211        defined; the 1st five and last two should be reserved for internal program
00212        use (esp. the last two). The INIT set should be set to represent the entire
00213        module set. */
00214     #define N_MASK_SETS   8
00215         #define MASK_SET_0     0       //Note: Used by calibration routines.
00216         #define MASK_SET_1     1       //              ""
00217         #define MASK_SET_2     2       //              ""
00218         #define MASK_SET_3     3       //              ""
00219         #define MASK_SET_USER  4       //General purpose.
00220         #define MASK_SET_INIT  5       //Should be set using a primlist on startup.
00221 
00222         /* Work0 & 1 are general purpose; note however that they are used internally
00223            as well and so their values should not be counted on to stay constant, esp.
00224            during complex operations. */
00225         #define MASK_SET_WORK0 6
00226         #define MASK_SET_WORK1 7
00227 
00228         #define MASK_SET_ALL   8       
00229 
00230         #define MASK_SET_SEARCH  9  //Used internally.
00231 
00232     typedef struct MaskConfigData {
00233         CmdMask   cmdMask[2]; /* [0]= default / SP0  [1]= crtv. / SP1 */ 
00234         DynMask   dynMask[2];   
00235         FmtMask   fmtMask;
00236 
00237         /* Bitfield defining which modules are contained in the mask set; there are
00238            separate sets for the command masks and mode bits. The link configuration
00239            is not handled, since during mask operations normally just the command
00240            links & mode bits are changed and link configuration is left alone. */
00241         UINT32    validModules[2][2];
00242         
00243         /* Used for diagnostics: set the output of the LEMO connector on the ROD
00244            front panel to the lowermost link of last module updated in the set. */
00245         UINT32    lemoLink, lemoFmt, unused[2];
00246 
00247         DeltaMask deltaMask[N_MASK_SETS];
00248     } MaskConfigData;
00249 
00250 #endif
00251 
00252 /* An array of ModuleMaskData (defined in the c file) stores the mask configuration
00253    for each module. This data copies a small subset of the full module configuration
00254    data; the data is used by both the MDSP and SDSPs. */
00255 typedef struct ModuleMaskData {
00256     UINT8 defined;
00257     UINT8 cmdLine;
00258     UINT8 fmtLink[2];
00259 } ModuleMaskData;
00260 
00261 typedef struct {
00262     UINT32 *buffPtr, nEvents, length;
00263 } InmemTrap;
00264 
00265 #endif

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