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simulation.h

00001 #if (defined(SIM))
00002 #ifndef SIMULATION_H     /* multiple inclusion protection */
00003 #define SIMULATION_H
00004 #include "memoryPartitions.h"
00005 
00006 void simPreInit(void);  //Runs before the main initialization routine.
00007 void simInit1(void);    //For quick tests
00008 void simSetup(void);    //performs setup of the async interrupt
00009 void simInit(void);     //More simulation setup.
00010 
00011 //Check for actions which are taken by the FPGAs on certain register accesses:
00012 void simFpgaCheck(UINT8 fRead, UINT32 reg, UINT32 wid, UINT32 bit, UINT32 val);
00013 
00014 //Arm the simulation routines so that the will simulate passage of an 'event':
00015 void simTriggerArm(UINT32 sdsp);
00016 
00017 /* Two macros which allow pausing & resuming the DSP timers quickly (these
00018    are faster than the CSL function calls TIMER_pause/resume). */
00019 #define pauseTimer(i)   (*((UINT32 *) (0x01940000 +(i<<18)))&= ~0x80);
00020 #define resumeTimer(i)  (*((UINT32 *) (0x01940000 +(i<<18)))|=  0x80);
00021 
00022 #if (defined(I_AM_MASTER_DSP))
00023     //Inlined versions of the SDSP comm. register fxns:
00024     static inline uint32 getSdspRegI(UINT32 sdsp, UINT32 addr) {
00025         uint32 *sdspAddr;
00026         //the mask removes any part of the address which is > 32 words:
00027         sdspAddr= (UINT32 *) (SIM_SDSP_REG_BASE(sdsp) +(addr & 0x7f));
00028         return *sdspAddr;
00029     }
00030 #endif
00031 
00032 #endif   /* Multiple inclusion protection */
00033 #endif

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