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00019 #ifndef COM_REG_DFNS
00020 #define COM_REG_DFNS
00021
00022 #include "txtBuffer.h"
00023 #include "rodConfiguration.h"
00024
00025
00026
00027
00028
00029
00030
00031
00032
00033
00034
00035
00036
00037
00038
00039 #if defined(I_AM_HOST)
00040 #define IDREGS_BASE 0x80000000
00041 #endif
00042
00043
00044
00045
00046
00047
00048 #if defined(SCT_ROD)
00049 #include "comRegDfns_11x.h"
00050
00051 #elif defined(PIXEL_ROD)
00052 typedef struct {
00053 UINT32 status[2];
00054 UINT32 listStatus;
00055 UINT32 listCnt;
00056
00057 UINT32 command;
00058 UINT32 taskState;
00059 UINT32 memoryMap;
00060 UINT32 time;
00061
00062 UINT32 diagnostic;
00063 UINT32 hCmd;
00064 UINT32 hStat[2];
00065
00066 UINT32 hSdspStat[4];
00067
00068 UINT32 trapCmd;
00069 UINT32 trapStat[3];
00070
00071 UINT32 reservedReg[8];
00072
00073 UINT32 trapReq;
00074 UINT32 loop;
00075
00076
00077
00078
00079
00080 #if (defined(I_AM_HOST))
00081 UINT32 privateDsp[2];
00082 #elif (defined(I_AM_MASTER_DSP))
00083 UINT32 interDspHshkWr, interDspHshkRd;
00084 #elif (defined(I_AM_SLAVE_DSP))
00085 UINT32 interDspHshkRd, interDspHshkWr;
00086 #endif
00087
00088 } CommRegs;
00089
00090
00091
00092 #define STATUS_REG_0 (IDREGS_BASE) // pixel ROD only!
00093 #define STATUS_REG_2 ((STATUS_REG_0) + 4)
00094 #define LIST_STATUS_REG ((STATUS_REG_2) + 4)
00095 #define LIST_CNT_REG ((LIST_STATUS_REG) + 4)
00096
00097
00098 #define COMMAND_REG_0 ((LIST_CNT_REG) + 4) // pixel ROD only!
00099 #define TASK_STATE_REG ((COMMAND_REG_0) + 4)
00100 #define MEMORY_MAP_REG ((TASK_STATE_REG) + 4)
00101 #define EXTRA_REG ((MEMORY_MAP_REG) + 4)
00102
00103
00104 #define DIAGNOSTIC_REG ((EXTRA_REG) + 4) // pixel ROD only!
00105 #define HCMD_REG ((DIAGNOSTIC_REG) + 4)
00106 #define HSTATUS_REG_0 ((HCMD_REG) + 4)
00107 #define HSTATUS_REG_1 ((HSTATUS_REG_0) + 4)
00108
00109 #define HCMD_STAT_REG_0 (HCMD_REG) // pixel ROD only!
00110 #define HSTAT_REG_0 (HSTATUS_REG_0)
00111 #define HSTAT_REG_1 (HSTATUS_REG_1)
00112 #define HCMD_STAT_REG_1 (EXTRA_REG)
00113
00114
00115 #define HSSTAT_REG_0 ((HSTATUS_REG_1) + 4) // pixel ROD only!
00116 #define HSSTAT_REG_1 ((HSSTAT_REG_0) + 4)
00117 #define HSSTAT_REG_2 ((HSSTAT_REG_1) + 4)
00118 #define HSSTAT_REG_3 ((HSSTAT_REG_2) + 4)
00119
00120
00121 #if ((defined(I_AM_MASTER_DSP)) || (defined(I_AM_HOST)))
00122 #define SDSP_HSTATUS_REG_2 (HSSTAT_REG_0)
00123 #define SDSP_HSTATUS_REG_3 (HSSTAT_REG_1)
00124 #define SDSP_HSTATUS_REG_4 (HSSTAT_REG_2)
00125 #define SDSP_HSTATUS_REG_5 (HSSTAT_REG_3)
00126
00127 #elif (defined(I_AM_SLAVE_DSP))
00128 #define HSTATUS_REG_2 (HSSTAT_REG_0)
00129 #define HSTATUS_REG_3 (HSSTAT_REG_1)
00130 #define HSTATUS_REG_4 (HSSTAT_REG_2)
00131 #define HSTATUS_REG_5 (HSSTAT_REG_3)
00132 #endif
00133
00134
00135 #define TRAP_CMD_REG ((HSSTAT_REG_3) + 4)
00136 #define TRAPSTAT_REG_0 ((TRAP_CMD_REG) + 4)
00137 #define TRAPSTAT_REG_1 ((TRAPSTAT_REG_0) + 4)
00138 #define TRAPSTAT_REG_2 ((TRAPSTAT_REG_1) + 4)
00139
00140
00141 #define TRAP_CMD_STAT (TRAP_CMD_REG)
00142
00143
00144 #define RESERVED_REG_0 ((TRAPSTAT_REG_2) + 4)
00145 #define RESERVED_REG_1 ((RESERVED_REG_0) + 4)
00146 #define RESERVED_REG_2 ((RESERVED_REG_1) + 4)
00147 #define RESERVED_REG_3 ((RESERVED_REG_2) + 4)
00148
00149
00150 #define RESERVED_REG_4 ((RESERVED_REG_3) + 4)
00151 #define RESERVED_REG_5 ((RESERVED_REG_4) + 4)
00152 #define RESERVED_REG_6 ((RESERVED_REG_5) + 4)
00153 #define RESERVED_REG_7 ((RESERVED_REG_6) + 4)
00154
00155
00156 #define TRAP_REQ_REG ((RESERVED_REG_7) + 4)
00157 #define LOOP_REG ((TRAP_REQ_REG) + 4)
00158
00159
00160 #if defined(I_AM_HOST)
00161 #define PRIVATE_DSP_0 ((LOOP_REG) + 4)
00162 #define PRIVATE_DSP_1 ((PRIVATE_DSP_0) + 4)
00163 #elif defined(I_AM_MASTER_DSP)
00164 #define INTR_DSP_HSHK_WR ((LOOP_REG) + 4)
00165 #define INTR_DSP_HSHK_RD ((INTR_DSP_HSHK_WR) + 4)
00166 #elif defined(I_AM_SLAVE_DSP)
00167 #define INTR_DSP_HSHK_RD ((LOOP_REG) + 4)
00168 #define INTR_DSP_HSHK_WR ((INTR_DSP_HSHK_RD) + 4)
00169 #endif
00170
00171 #endif //SCT or Pixel ROD
00172
00173
00174
00175 #define SR_RUNNING 0
00176 #define SR_BUSY 1
00177 #define SR_EXECUTING 2
00178 #define SR_PAUSED 3
00179
00180 #define SR_OUT_LIST_RDY 4
00181 #define SR_DSP_ACK 5
00182 #define SR_DMA_ACCESS_ACK 6
00183 #define SR_DMA_ACCESS_ERR 7
00184
00185 #define SR_TXT_BUFF_NE(x) (8 + (x))
00186 #define SR_TXT_BUFF_PROC(x) (12 + (x))
00187
00188 #define SR_NTASKS 16
00189 #define SR_NTASKS_W 4
00190
00191 #define SR_IDLS_ACTIVE 20
00192 #define SR_EVM 21
00193 #define SR_IDLP_ACTIVE 21
00194 #define SR_LISTERR 22
00195 #define SR_LISTFATAL 23
00196
00197
00198 #define SR_CACHE_ACTIVE 27
00199
00200 #define SR_DSP_WAITING 28
00201 #define SR_INMEM_BUFF_ACK 29
00202 #define SR_INIT_ERROR 30
00203 #define SR_EMIF_ERROR 31
00204
00205
00206 #if (defined(I_AM_MASTER_DSP) || defined(I_AM_HOST))
00207 #define SR_SLVCOMM(x) (x)
00208 #define SR_HLTS(x) (4 + (x))
00209 #define SR_SLVATTEND 8
00210 #endif
00211
00212
00213 #define ATTN_IFRAME_CNT 0
00214 #define ATTN_SLOW_DATA 1
00215 #define ATTN_ERR_EVT 2
00216 #define ATTN_BUFF_OVF 3
00217
00218
00219
00220 #if defined(SCT_ROD)
00221
00222 #define SR_PRIM_LIST_INDEX 0
00223 #define SR_PRIM_LIST_INDEX_W 4
00224 #define SR_PRIM_INDEX 4
00225 #define SR_PRIM_INDEX_W 20
00226
00227
00228 #define LCR_PRIM_INDEX (SR_PRIM_INDEX)
00229 #define LCR_PRIM_INDEX_W (SR_PRIM_INDEX_W)
00230 #define LCR_ERR_INDEX 24
00231 #define LCR_ERR_INDEX_W 8
00232 #define LCR_LIST_INDEX (SR_PRIM_LIST_INDEX)
00233 #define LCR_LIST_INDEX_W (SR_PRIM_LIST_INDEX_W)
00234
00235 #elif defined(PIXEL_ROD)
00236
00237 #define LCR_PRIM_INDEX 0
00238 #define LCR_PRIM_INDEX_W 12
00239 #define LCR_ERR_INDEX 12
00240 #define LCR_ERR_INDEX_W 12
00241 #define LCR_LIST_INDEX 24
00242 #define LCR_LIST_INDEX_W 8
00243
00244 #endif
00245
00246
00247 #define CR_IN_LIST_RDY 0
00248 #define CR_PAUSE 1
00249 #define CR_RESUME 2
00250 #define CR_ABORT 3
00251 #define CR_TXT_BUFF_RR(x) (4 + (x))
00252 #define CR_RESET_INMEM_BUFF 8
00253 #define CR_DMA_ACCESS_REQ 10
00254 #define CR_FLUSH_EVENTS 11
00255 #define CR_IDLP_ACTIVE 12
00256 #define CR_ID 28
00257 #define CR_ID_W 2
00258
00259 #define CR_HISTO_OVERRIDE 13
00260
00261
00262 #define CR_RST_ATTN_IFRAME_CNT 16 +(ATTN_IFRAME_CNT)
00263 #define CR_RST_ATTN_SLOW_DATA 16 +(ATTN_SLOW_DATA)
00264 #define CR_RST_ATTN_ERR_EVT 16 +(ATTN_ERR_EVT)
00265 #define CR_RST_ATTN_BUFF_OVF 16 +(ATTN_BUFF_OVF)
00266
00267
00268 #define TASK_STATE(x) (4*x)
00269 #define TASK_STATE_W 4
00270
00271
00272
00273
00274
00275 #define DR_DISP_ROD_REG_ID 0 //MDSP
00276 #define DR_LOOPEVENT 0 //SDSP
00277 #define DR_DISP_SERIAL_LOOPS 1
00278 #define DR_USE_MDSP_MASK_LUT 2 //MDSP
00279 #define DR_HISTO_1 2 //SDSP
00280 #define DR_HISTO_3 3 //SDSP
00281 #define DR_SCAN_LEMO 3 //MDSP
00282 #define DR_DISP_MIRROR_CTIME 4
00283 #define DR_SCAN_DELAY 5 //MDSP
00284
00285 #define DR_STEP_CTRL 6
00286 #define DR_STEP_TRIGGER 7
00287 #define DR_PASSON 8
00288 #define DR_SOFT_BC_RESET 9
00289 #define DR_HTYPE_REGSET 10
00290 #define DR_HISTO_CHIPOCC 11
00291 #define DR_MAINLOOP_TOGGLE 12
00292
00293 #define DR_PROCWAIT 13
00294 #define DR_TRIG_PAUSE 14 //MDSP
00295 #define DR_TRIGWAIT 15 //MDSP
00296 #define DR_HISTO_ASM 15
00297 #define DR_INFO_DISPLAY 16
00298 #define DR_MODULE_CFG_LOOP 17
00299 #define DR_SLAVE_WRITE_TEST 18
00300 #define DR_CACHE_FLUSH 17 //SDSP
00301 #define DR_CACHE_RANGE_FLUSH 18 //SDSP
00302 #define DR_CACHE_TOGGLE 19 //SDSP
00303
00304 #define DR_ISR_DELAY 19
00305 #define DR_DISP_LINK_DATA 20
00306 #define DR_AUTO_STALL 21 //MDSP
00307 #define DR_STAGE_PAUSE 22 //MDSP
00308 #define DR_CAL_EVT_CAPTURE 23
00309 #define DR_BIN_PAUSE 24
00310 #define DR_NOMASKSET 25
00311 #define DR_TRIGGER_SERIES 26
00312 #define DR_REGULATE_TRIGGER 27
00313
00314 #define DR_SPEED_220 30
00315 #define DR_RESET_FIFOS 31
00316
00317
00318 #if (defined(I_AM_MASTER_DSP) || defined(I_AM_HOST))
00319 #define HCMD_EXE 0
00320 #define HCMD_BINADVANCE 1
00321 #define HCMD_STAGEADVANCE 2
00322 #define HCMD_SWITCHMASK 3
00323 #define HCMD_MASK 4
00324 #define HCMD_MASK_W 4
00325 #define HCMD_CHIPADVANCE 8
00326 #define HCMD_CFG_NORM 9
00327 #define HCMD_CFG_OFFROD 10
00328
00329 #define HSTAT0_BIN 0
00330 #define HSTAT0_BIN_W 8
00331 #define HSTAT0_CHIP 8
00332 #define HSTAT0_CHIP_W 8
00333 #define HSTAT0_STAGE 16
00334 #if (defined(SCT_ROD))
00335 #define HSTAT0_STAGE_W 4
00336 #elif (defined(PIXEL_ROD))
00337 #define HSTAT0_STAGE_W 12
00338 #endif
00339 #define HSTAT0_ACK 28
00340
00341 #define HSTAT1_NERR 0
00342 #define HSTAT1_NERR_W 8
00343 #define HSTAT1_AVGTRAN 8
00344 #define HSTAT1_AVGTRAN_W 8
00345 #define HSTAT1_AVGPROC 16
00346 #define HSTAT1_AVGPROC_W 16
00347 #endif
00348
00349
00350
00351 #define HCMD_SLV_BIN 0
00352 #define HCMD_SLV_BIN_W 8
00353 #define HCMD_SLV_NEWBIN 8
00354
00355 #define HCMD_SLV_STAGE 16
00356 #if (defined(SCT_ROD))
00357 #define HCMD_SLV_STAGE_W 4
00358 #elif (defined(PIXEL_ROD))
00359 #define HCMD_SLV_STAGE_W 12
00360 #endif
00361
00362 #define HSR0_SLV_RDY 0
00363 #define HSR0_SLV_EXP 1
00364 #define HSR0_SLV_PROC 2
00365 #define HSR0_SLV_DONE 3
00366 #define HSR0_SLV_PBIN 4
00367 #define HSR0_SLV_HFIT 5
00368 #define HSR0_SLV_WARN 6
00369 #define HSR0_SLV_WARN_W 2
00370 #define HSR0_SLV_BIN 8
00371 #define HSR0_SLV_BIN_W 8
00372 #define HSR0_SLV_BINERR 16
00373 #define HSR0_SLV_BINERR_W 8
00374
00375 #define HSR1_SLV_NEVTBIN 0
00376 #define HSR1_SLV_NEVTBIN_W 32
00377
00378 #define HSR2_SLV_IDLECNT 0
00379 #define HSR2_SLV_IDLECNT_W 32
00380
00381 #define HSR3_SLV_PROCTIME 0
00382 #define HSR3_SLV_PROCTIME_W 32
00383
00384
00385 #define HCSR0_SLV_BIN (HCMD_SLV_BIN)
00386 #define HCSR0_SLV_BIN_W (HCMD_SLV_BIN_W)
00387 #define HCSR0_SLV_NEWBIN (HCMD_SLV_NEWBIN)
00388 #define HCSR0_SLV_CALLINE_EN (HCMD_SLV_NEWBIN +1)
00389 #define HCSR0_SLV_NEWCAL (HCMD_SLV_NEWBIN +2)
00390 #define HCSR0_SLV_CALLINE (HCMD_SLV_STAGE)
00391 #define HCSR0_SLV_CALLINE_W (HCMD_SLV_STAGE_W)
00392 #define HCSR1_SLV_BINEVT (HSR1_SLV_NEVTBIN)
00393
00394
00395
00396 #define TCMD_EVTSERIES 4
00397 #define TCMD_EVTSERIES_W 4
00398
00399
00400 #define TSR0_TRAILER 0
00401 #define TSR0_TRANSMIT 1
00402 #define TSR0_HEADER 2
00403 #define TSR0_ISR_ACTIVE 3
00404
00405 #define TSR0_EVTSERIES 4
00406 #define TSR0_EVTSERIES_W 4
00407
00408 #define TSR0_OVERFLOW_ARM 8
00409 #define TSR0_OVERFLOW 9
00410 #define TSR0_TRAILER_ERROR 10
00411 #define TSR0_HEADER_ERROR 11
00412
00413 #define TSR0_L1ID_ERROR 12
00414 #define TSR0_BCID_ERROR 13
00415 #define TSR0_DATA_ERROR 14
00416 #define TSR0_ERROR 15
00417
00418 #define TSR0_EVT_WORD_CNT 16
00419 #define TSR0_EVT_WORD_CNT_W 16
00420
00421
00422
00423 #define TSR1_ERR_COUNT 0
00424 #define TSR1_ERR_COUNT_W 16
00425
00426 #define TSR1_EVT_COUNT 16
00427 #define TSR1_EVT_COUNT_W 16
00428
00429
00430
00431 #define TSR2_IFRAME_TAIL 0
00432 #define TSR2_IFRAME_TAIL_W 8
00433 #define TSR2_IFRAME_HEAD 8
00434 #define TSR2_IFRAME_HEAD_W 8
00435
00436 #define TSR2_XFRAME_TAIL 16
00437 #define TSR2_XFRAME_TAIL_W 8
00438 #define TSR2_XFRAME_HEAD 24
00439 #define TSR2_XFRAME_HEAD_W 8
00440
00441
00442
00443
00444
00445
00446 #define INTR_DSP_IN_LIST_RDY 0
00447 #define INTR_DSP_ABORT 1
00448 #define INTR_DSP_ACK 2
00449 #define INTR_DSP_OUT_LIST_RDY 3
00450 #define INTR_DSP_LIST_ERR 4
00451 #define INTR_DSP_LIST_FATAL 5
00452
00453 #endif