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TimDefine.h

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00001 //File: TimDefine.h
00002 
00003 #ifndef SCTPIXELROD_TIMDEFINE_H
00004 #define SCTPIXELROD_TIMDEFINE_H
00005 
00044 namespace SctPixelRod {
00045 
00046 #include "processor.h"
00047 
00049 
00050 enum TimTimingSCT {
00051      TIM_L1A_DEADTIME =  3,
00052      TIM_ECR_DEADTIME =  7,
00053      TIM_BCR_DEADTIME =  7,
00054      TIM_CAL_DEADTIME = 27,
00055      TIM_BCID_OFFSET  =  6
00056 };
00057 
00058 const INT32 TIM_L1ID_FIRST = 0; 
00059 
00063 const INT32 TIM_SEQ_SIZE = 0x4000; 
00064 const INT32 TIM_SEQ_ADDR = 0x8000; 
00065 
00067 //The first of an identical pair is the old name.
00068 
00069 enum TimRegister {
00070       TIM_REG_ENABLES      = 0x00,
00071       TIM_REG_COMMAND      = 0x02,
00072       TIM_REG_BURST_COUNT  = 0x04,
00073       TIM_REG_BURST        = 0x04,
00074       TIM_REG_FREQUENCY    = 0x06,
00075       TIM_REG_WINDOW       = 0x08,
00076       TIM_REG_DELAY        = 0x0A,
00077       TIM_REG_DELAYS       = 0x0A,
00078       TIM_REG_STATUS       = 0x0C,
00079       TIM_REG_FIFO_STATUS  = 0x0E,
00080       TIM_REG_FIFO         = 0x0E,
00081       TIM_REG_TRIGGER_IDLO = 0x10,
00082       TIM_REG_L1IDL        = 0x10,
00083       TIM_REG_TRIGGER_IDHI = 0x12,
00084       TIM_REG_L1IDH        = 0x12,
00085       TIM_REG_TRIGGER_BCID = 0x14,
00086       TIM_REG_BCID         = 0x14,
00087       TIM_REG_TRIGGER_TYPE = 0x16,
00088       TIM_REG_TTID         = 0x16,
00089       TIM_REG_RUN_ENABLES  = 0x18,
00090       TIM_REG_RUN_ENABLE   = 0x18,
00091       TIM_REG_SEQ_CONTROL  = 0x1A,
00092       TIM_REG_SEQ_CTL      = 0x1A,
00093       TIM_REG_SEQ_END      = 0x1C,
00094       TIM_REG_ROD_MASK     = 0x1E,
00095       TIM_REG_RB_MASK      = 0x1E,
00096       TIM_REG_ROD_BUSY     = 0x20,
00097       TIM_REG_RB_STAT      = 0x20,
00098       TIM_REG_ROD_LATCH    = 0x22,
00099       TIM_REG_RB_LATCH     = 0x22,
00100       TIM_REG_ROD_MONITOR  = 0x24,
00101       TIM_REG_RB_MON       = 0x24,
00102       TIM_REG_TTC_DATA     = 0x26,
00103       TIM_REG_TTC_SELECT   = 0x28,
00104       TIM_REG_TTC_BCID     = 0x2A,
00105       TIM_REG_TTC_RX       = 0x2C,
00106       TIM_REG_TTCRX_CTL    = 0x2C,
00107       TIM_REG_TTC_STATUS   = 0x2E,
00108       TIM_REG_OUTPUT       = 0x30,
00109       TIM_REG_TIM_OUTPUT   = 0x30,
00110       TIM_REG_TIM_ID       = 0x32,
00111 
00112       TIM_REG_ENABLES3     = 0x42,
00113 
00114       TIM_REG_CONTROL      = 0x46,
00115 
00116       TIM_REG_STATUS3      = 0x4A,
00117       TIM_REG_STATUS_LCH   = 0x4C,
00118       TIM_REG_STAT3_LCH    = 0x4E,
00119 
00120       TIM_REG_QPLL_CTL     = 0x52,
00121 
00122       TIM_REG_BUSY_EN3     = 0x56,
00123 
00124       TIM_REG_BUSY_STAT3   = 0x5A,
00125 
00126       TIM_REG_BSTAT3_LCH   = 0x5E,
00127       TIM_REG_BCOUNTL      = 0x60,
00128       TIM_REG_BCOUNTH      = 0x62,
00129       TIM_REG_BCOUNTX      = 0x64,
00130 
00131       TIM_REG_FV_VETOLEN   = 0x68,
00132       TIM_REG_FV_MATCH     = 0x6A,
00133       TIM_REG_FV_P_MIN     = 0x6C,
00134       TIM_REG_FV_P_MAX     = 0x6E,
00135       TIM_REG_FV_OFLOW     = 0x70,
00136       TIM_REG_FV_DELTAT    = 0x72,
00137       TIM_REG_FV_COUNTL    = 0x74,
00138       TIM_REG_FV_COUNTH    = 0x76,
00139       TIM_REG_FV_COUNTX    = 0x78,
00140 
00141       TIM_REG_FV_TCOUNTL   = 0x7C,
00142       TIM_REG_FV_TCOUNTH   = 0x7E,
00143       TIM_REG_TP_FIFOL     = 0x80,
00144       TIM_REG_TP_FIFOH     = 0x82,
00145       TIM_REG_FV_IDL       = 0x84,
00146       TIM_REG_FV_IDH       = 0x86,
00147 
00148 
00149 
00150       TIM_REG_BURST_HI     = 0x8E,
00151       TIM_REG_TT_COUNT     = 0x90,
00152       TIM_REG_TTS_COUNT    = 0x92,
00153       TIM_REG_TSTAMPL      = 0x94,
00154       TIM_REG_TSTAMPH      = 0x96,
00155       TIM_REG_SRC_ADDR     = 0x98,
00156       TIM_REG_SINK_ADDR    = 0x9A,
00157       TIM_REG_DEBUG_CTL    = 0x9C,
00158       TIM_REG_DEBUG_STAT   = 0x9E
00159 }; 
00160 
00162 
00163 enum TimBitEnables {
00164      TIM_BIT_EN_INT_TRIG = 0x0002,  
00165      TIM_BIT_EN_INT_ECR  = 0x0004,  
00166      TIM_BIT_EN_INT_BCR  = 0x0008,  
00167      TIM_BIT_EN_RANDOM   = 0x0010,  
00168      TIM_BIT_EN_INT_FER  = 0x0020,  
00169      TIM_BIT_EN_WINDOW   = 0x0040,  
00170      TIM_BIT_EN_INT_BUSY = 0x0080,  
00171 
00172      TIM_BIT_EN_EXT_CLK  = 0x0100,  
00173      TIM_BIT_EN_EXT_TRIG = 0x0200,  
00174      TIM_BIT_EN_EXT_ECR  = 0x0400,  
00175      TIM_BIT_EN_EXT_BCR  = 0x0800,  
00176      TIM_BIT_EN_EXT_CAL  = 0x1000,  
00177      TIM_BIT_EN_EXT_FER  = 0x2000,  
00178      TIM_BIT_EN_EXT_SEQ  = 0x4000,  
00179      TIM_BIT_EN_EXT_BUSY = 0x8000   
00180 };
00181 
00183 enum TimBitBackplane {
00184      TIM_L1A = 0x01,       
00185      TIM_ECR = 0x02,       
00186      TIM_BCR = 0x04,       
00187      TIM_CAL = 0x08,       
00188      TIM_SID = 0x10,       
00189      TIM_STT = 0x20,       
00190      TIM_CMD = 0xCF,       
00191      TIM_RES = 0xC0,       
00192      TIM_FER = 0x40,       
00193      TIM_SPA = 0x80,       
00194      TIM_TRG = 0x31        
00195 };
00197 enum TimBitCommand {
00198      TIM_VTRG = 0x02,      
00199      TIM_VECR = 0x04,      
00200      TIM_VBCR = 0x08,      
00201      TIM_VCAL = 0x10,      
00202      TIM_VFER = 0x20,      
00203      TIM_VSPA = 0x40,      
00204 
00205      TIM_BIT_EN_TTC = 0x1000,      
00206      TIM_BIT_VRESET = 0x8000
00207 };
00208 
00209 enum TimBitRunEnables {
00210      TIM_BIT_EN_ID   = 0x0200,
00211      TIM_BIT_EN_TYPE = 0x0400
00212 };
00213 
00214 enum TimBitSeqControl {
00215      TIM_BIT_SEQ_EN_ALL = 0x00FF,
00216      TIM_BIT_SEQ_RESET  = 0x0200,
00217      TIM_BIT_SEQ_GO     = 0x0400,
00218      TIM_BIT_EN_CYCLIC  = 0x0800
00219 };
00220 
00221 enum TimBitTTCStatus {
00222      TIM_BIT_TTC_READY  = 0x4000
00223 };
00225 
00226 enum TimBitStatus3 {
00227      TIM_BIT_STATUS3_TTCCLKENOK = 0x0080,
00228      TIM_BIT_STATUS3_EXTCLKENOK = 0x0100,
00229      TIM_BIT_STATUS3_INTCLKENOK = 0x0200,
00230      TIM_BIT_STATUS3_PLLSTABLE  = 0x0400
00231 };
00232 
00233 enum TimBitBusyEnable3 {
00234      TIM_BIT_BUSY_EN3_ENRBBUSY  = 0x0001
00235 };
00236 
00237 enum TimBitDebugCtl {
00238      TIM_BIT_DEBUGCTL_CSBDISABLE = 0x0100,
00239      TIM_BIT_DEBUGCTL_FVDISABLE  = 0x1000
00240 };
00241 
00243 
00245 
00246 enum TimMaskFrequency {
00247      TIM_MASK_TRIG_600_KHZ = 0x0000,
00248      TIM_MASK_TRIG_300_KHZ = 0x0002,
00249      TIM_MASK_TRIG_200_KHZ = 0x0003,
00250      TIM_MASK_TRIG_150_KHZ = 0x0004,
00251      TIM_MASK_TRIG_120_KHZ = 0x0005,
00252      TIM_MASK_TRIG_100_KHZ = 0x0006,
00253      TIM_MASK_TRIG_60_0KHZ = 0x0001,
00254      TIM_MASK_TRIG_50_0KHZ = 0x0007,
00255      TIM_MASK_TRIG_30_0KHZ = 0x000A,
00256      TIM_MASK_TRIG_20_0KHZ = 0x000B,
00257      TIM_MASK_TRIG_15_0KHZ = 0x000C,
00258      TIM_MASK_TRIG_12_0KHZ = 0x000D,
00259      TIM_MASK_TRIG_10_0KHZ = 0x000E,
00260      TIM_MASK_TRIG_6_00KHZ = 0x0009,
00261      TIM_MASK_TRIG_5_00KHZ = 0x000F,
00262      TIM_MASK_TRIG_3_00KHZ = 0x0012,
00263      TIM_MASK_TRIG_2_00KHZ = 0x0013,
00264      TIM_MASK_TRIG_1_50KHZ = 0x0014,
00265      TIM_MASK_TRIG_1_20KHZ = 0x0015,
00266      TIM_MASK_TRIG_1_00KHZ = 0x0016,
00267      TIM_MASK_TRIG_0_60KHZ = 0x0011,
00268      TIM_MASK_TRIG_0_50KHZ = 0x0017,
00269      TIM_MASK_TRIG_0_30KHZ = 0x001A,
00270      TIM_MASK_TRIG_0_20KHZ = 0x001B,
00271      TIM_MASK_TRIG_0_15KHZ = 0x001C,
00272      TIM_MASK_TRIG_0_12KHZ = 0x001D,
00273      TIM_MASK_TRIG_0_10KHZ = 0x001E,
00274      TIM_MASK_TRIG_0_06KHZ = 0x0019,
00275      TIM_MASK_TRIG_0_05KHZ = 0x001F,
00276 
00277      TIM_MASK_FECR_60_00HZ = 0x0000,
00278      TIM_MASK_FECR_30_00HZ = 0x0200,
00279      TIM_MASK_FECR_20_00HZ = 0x0300,
00280      TIM_MASK_FECR_15_00HZ = 0x0400,
00281      TIM_MASK_FECR_12_00HZ = 0x0500,
00282      TIM_MASK_FECR_10_00HZ = 0x0600,
00283      TIM_MASK_FECR_6_000HZ = 0x0100,
00284      TIM_MASK_FECR_5_000HZ = 0x0700,
00285      TIM_MASK_FECR_3_000HZ = 0x0A00,
00286      TIM_MASK_FECR_2_000HZ = 0x0B00,
00287      TIM_MASK_FECR_1_500HZ = 0x0C00,
00288      TIM_MASK_FECR_1_200HZ = 0x0D00,
00289      TIM_MASK_FECR_1_000HZ = 0x0E00,
00290      TIM_MASK_FECR_0_600HZ = 0x0900,
00291      TIM_MASK_FECR_0_500HZ = 0x0F00,
00292      TIM_MASK_FECR_0_300HZ = 0x1200,
00293      TIM_MASK_FECR_0_200HZ = 0x1300,
00294      TIM_MASK_FECR_0_150HZ = 0x1400,
00295      TIM_MASK_FECR_0_120HZ = 0x1500,
00296      TIM_MASK_FECR_0_100HZ = 0x1600,
00297      TIM_MASK_FECR_0_060HZ = 0x1100,
00298      TIM_MASK_FECR_0_050HZ = 0x1700,
00299      TIM_MASK_FECR_0_030HZ = 0x1A00,
00300      TIM_MASK_FECR_0_020HZ = 0x1B00,
00301      TIM_MASK_FECR_0_015HZ = 0x1C00,
00302      TIM_MASK_FECR_0_012HZ = 0x1D00,
00303      TIM_MASK_FECR_0_010HZ = 0x1E00,
00304      TIM_MASK_FECR_0_006HZ = 0x1900,
00305      TIM_MASK_FECR_0_005HZ = 0x1F00
00306 };
00307 
00308 const int TIM_FREQ_SIZE = 29;
00309 
00310 const int TIM_TRIG_FREQUENCY[TIM_FREQ_SIZE][2] = {
00311    { TIM_MASK_TRIG_600_KHZ, 600000 },
00312    { TIM_MASK_TRIG_300_KHZ, 300000 },
00313    { TIM_MASK_TRIG_200_KHZ, 200000 },
00314    { TIM_MASK_TRIG_150_KHZ, 150000 },
00315    { TIM_MASK_TRIG_120_KHZ, 120000 },
00316    { TIM_MASK_TRIG_100_KHZ, 100000 },
00317    { TIM_MASK_TRIG_60_0KHZ,  60000 },
00318    { TIM_MASK_TRIG_50_0KHZ,  50000 },
00319    { TIM_MASK_TRIG_30_0KHZ,  30000 },
00320    { TIM_MASK_TRIG_20_0KHZ,  20000 },
00321    { TIM_MASK_TRIG_15_0KHZ,  15000 },
00322    { TIM_MASK_TRIG_12_0KHZ,  12000 },
00323    { TIM_MASK_TRIG_10_0KHZ,  10000 },
00324    { TIM_MASK_TRIG_6_00KHZ,   6000 },
00325    { TIM_MASK_TRIG_5_00KHZ,   5000 },
00326    { TIM_MASK_TRIG_3_00KHZ,   3000 },
00327    { TIM_MASK_TRIG_2_00KHZ,   2000 },
00328    { TIM_MASK_TRIG_1_50KHZ,   1500 },
00329    { TIM_MASK_TRIG_1_20KHZ,   1200 },
00330    { TIM_MASK_TRIG_1_00KHZ,   1000 },
00331    { TIM_MASK_TRIG_0_60KHZ,    600 },
00332    { TIM_MASK_TRIG_0_50KHZ,    500 },
00333    { TIM_MASK_TRIG_0_30KHZ,    300 },
00334    { TIM_MASK_TRIG_0_20KHZ,    200 },
00335    { TIM_MASK_TRIG_0_15KHZ,    150 },
00336    { TIM_MASK_TRIG_0_12KHZ,    120 },
00337    { TIM_MASK_TRIG_0_10KHZ,    100 },
00338    { TIM_MASK_TRIG_0_06KHZ,     60 },
00339    { TIM_MASK_TRIG_0_05KHZ,     50 }
00340 };
00341 
00342 const int TIM_FECR_FREQUENCY[TIM_FREQ_SIZE][2] = {
00343    { TIM_MASK_FECR_60_00HZ, 60000 },
00344    { TIM_MASK_FECR_30_00HZ, 30000 },
00345    { TIM_MASK_FECR_20_00HZ, 20000 },
00346    { TIM_MASK_FECR_15_00HZ, 15000 },
00347    { TIM_MASK_FECR_12_00HZ, 12000 },
00348    { TIM_MASK_FECR_10_00HZ, 10000 },
00349    { TIM_MASK_FECR_6_000HZ,  6000 },
00350    { TIM_MASK_FECR_5_000HZ,  5000 },
00351    { TIM_MASK_FECR_3_000HZ,  3000 },
00352    { TIM_MASK_FECR_2_000HZ,  2000 },
00353    { TIM_MASK_FECR_1_500HZ,  1500 },
00354    { TIM_MASK_FECR_1_200HZ,  1200 },
00355    { TIM_MASK_FECR_1_000HZ,  1000 },
00356    { TIM_MASK_FECR_0_600HZ,   600 },
00357    { TIM_MASK_FECR_0_500HZ,   500 },
00358    { TIM_MASK_FECR_0_300HZ,   300 },
00359    { TIM_MASK_FECR_0_200HZ,   200 },
00360    { TIM_MASK_FECR_0_150HZ,   150 },
00361    { TIM_MASK_FECR_0_120HZ,   120 },
00362    { TIM_MASK_FECR_0_100HZ,   100 },
00363    { TIM_MASK_FECR_0_060HZ,    60 },
00364    { TIM_MASK_FECR_0_050HZ,    50 },
00365    { TIM_MASK_FECR_0_030HZ,    30 },
00366    { TIM_MASK_FECR_0_020HZ,    20 },
00367    { TIM_MASK_FECR_0_015HZ,    15 },
00368    { TIM_MASK_FECR_0_012HZ,    12 },
00369    { TIM_MASK_FECR_0_010HZ,    10 },
00370    { TIM_MASK_FECR_0_006HZ,     6 },
00371    { TIM_MASK_FECR_0_005HZ,     5 }
00372 };
00373 
00374 } // End namespace SctPixelRod
00375 
00376 #endif // SCTPIXELROD_TIMDEFINE_H

Generated on Fri Dec 16 19:38:25 2005 for SCT DAQ/DCS Software - C++ by doxygen 1.3.5