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memoryPartitions.h

00001 /*************************************************************************************
00002  * memoryPartitions.h
00003  *
00004  *  synopsis: Defines the memory partitions in the DSP memory space.
00005  *            Declares routine for initializing memory.
00006  *            Should be included in the DSP and the VME host code.
00007  *
00008  *   In Project->Options->Compiler it is POSSIBLE to define
00009  *    TI_EVM: EVM DSP has smaller SDRAMs than the ROD DSPs. This option partitions
00010  *            memory accordingly.
00011  *    MAP_0: probably never used, ROD DSPs are wired for MAP_1, see peripherals 
00012  *           manual 10-5
00013  *    SIM:   If defined, handles some aspects of the DSP's environment (for SDSPs,
00014  *           this is the MDSP's responses to their communication register settings;
00015  *           for the MDSP this is the host's & SDSPs' responses. 
00016  *
00017  *  Damon Fasching, UW Madison                            fasching@wisconsin.cern.ch
00018  *  Douglas Ferguson, UW Madison   (510) 486-5230         dpferguson@lbl.gov
00019  *
00020  *  modifications/bugs    
00021  *   - Updated to reflect changes in the project organization. When BIOS was
00022  *     introduced, the program memory sections must be defined inside the config
00023  *     database; the MEMORY section of the linker command file is no longer used &
00024  *     is taken out. External code & data are combined and put the XPROG memory
00025  *     section (FARDATA gone). The default positions and sizes of the 4 text, and
00026  *     the primitive & reply buffers, have changed. 6701s now have 32M of external
00027  *     memory; 6201 still has 16M.                                      26.04.02 dpsf
00028  *
00029  *     n.b. Bios has now been removed as it is memory hungry & not
00030  *     essential.              dpsf
00031  *
00032  *   - Inter-DSP communication buffers put in SDRAM & communication registers moved
00033  *     to the beginning of internal memory (IDREG segment in the configuration
00034  *     database file) The 2 handshake registers have been left in internal memory
00035  *     with the other registers. A new section of memory, IDATA, has been created
00036  *     for important program variables; they should now remain relatively fixed in
00037  *     one spot instead of floating about in the program IDRAM while code is added
00038  *     & modified, as they did before. This is intended to be used with the
00039  *     DATA_SECTION pragma (see Optimizing C Compiler User's Guide, 7.6.4). Use of
00040  *     the pragma makes variables inaccessible to routines in other files, so
00041  *     use with care. (They can still be accessed by calling a function to return a
00042  *     pointer to them).                                                05.06.02 dpsf
00043  *
00044  *   - Added EXPERT, HCMD, HSTAT, TRAPREQ & TRAPSTAT registers for general purpose
00045  *     use, histogramming, and event trapping respectively. New defined locations in
00046  *     memory were added for the (suggested) base in memory of histograms & the
00047  *     trapping buffer as well.                                         20.06.02 dpsf
00048  *
00049  *   - New memory section MODULE_DATA was added for storage of new module
00050  *     configuration structures on the master.                          03.07.02 dpsf
00051  * 
00052  *   - Master & slave DSPs now have different size primitive & reply buffers. The
00053  *     compilation constants HOST_(PRM/REP)_BFR_(BASE/SZ) in memoryPartitions.h have
00054  *     been replaced with different sets for the two DSP types.        10.12.02 dpsf
00055  *
00056  *   - Removed unused options such as COMPACT compilation flag & DSP
00057  *     map 0 (ROD will use Map 1 only).                                22.02.04 dpsf
00058  *
00059  *   - Re-organization for use with the new ROD memory map & cleanup.  02.03.04 dpsf
00060  *************************************************************************************
00061  * NOTE: The segment sizes defined in this file for use in positioning registers and
00062  *       other program items (which are not explicitly declared as variables) must
00063  *   agree with the corresponding memory segment length and base, set in the
00064  *   linker command file.  **Otherwise overwrites are possible** The memory order of
00065  *   the segments defined there should be maintained as well. These segment sizes are:
00066  *
00067  *   IDREGS_SZ, IDATA_SZ, IDRAM_MEM_SZ, BURST_SZ, XPROG_SZ, and 
00068  *   (master only) MODULE_DATA_SZ
00069  *
00070  *   IDRAM_SZ is the total size of the DSP IDRAM.
00071  *   (IDRAM_MEM is used here for the memory section IDRAM in the linker command file).
00072  ************************************************************************************/
00073 #ifndef MEMORY_PARTITIONS
00074 #define MEMORY_PARTITIONS
00075 
00076 #include "processor.h"
00077 /*
00078  * On the Rev. B & C RODs, each DSP has 0x10000 bytes (64K) of internal program memory,
00079  * IPRAM, starting at 0x0, and 0x10000 bytes of internal data memory, IDRAM, starting
00080  * at 0x80000000 and 0x1000000 bytes (16M) SDRAM starting at 0x2000000 or 0x3000000.
00081  * On a Rev. E ROD, the SDSPs have a total of 256 KB internal memeory, which is shared
00082  * between program code & data, and 128 MB memory located on two of the CE spaces. The
00083  * MDSP is the same as the one on the previous revisions.
00084  *
00085  * Some of this is used for buffers and communication mailboxes whose addresses and
00086  * sizes are defined below.
00087  *
00088  *                      table of available memory spaces
00089  * Rev. B or C:
00090  *
00091  * mem space    base address             what's there for each device
00092  *
00093  *             MAP 1        EVM            MDSP           SDSPs
00094  * EMIF CE0  0x00400000  256KB SBSRAM  FPGA registers    ------
00095  * EMIF CE1  0x01400000                 boot ROM         router
00096  * EMIF CE2  0x02000000   4MB SDRAM    16MB SDRAM      16MB SDRAM
00097  * EMIF CE3  0x03000000   4MB SDRAM                    16MB SDRAM
00098  *  IPRAM    0x00000000          64KB internal program memory
00099  *  IDRAM    0x80000000          64KB intermal data memory   
00100  *
00101  * Rev. E or F SDSP (MDSP same as above):
00102  *             MAP 1         SDSPs
00103  * EMIF CE0  0x80000000     ------      
00104  * EMIF CE1  0x90000000     router      
00105  * EMIF CE2  0xA0000000   128 MB SDRAM
00106  * EMIF CE3  0xB0000000   128 MB SDRAM
00107  * IP/IDRAM  0x00000000   256 KB internal memory
00108  */
00109 
00110 /************************************************************************************
00111  *                  Base addresses of the available memories
00112  ************************************************************************************/
00113 
00114 /* internal program, internal data and 4 EMIF chip enables for off chip memories */
00115 #if ((defined(I_AM_MASTER_DSP))||(defined(I_AM_HOST)))
00116     #define CE0_BASE   (0x00400000)
00117     #define CE1_BASE   (0x01400000)
00118     #define IPRAM_BASE (0x00000000)
00119     
00120     #define CE2_BASE   (0x02000000)
00121     #define CE3_BASE   (0x03000000)
00122     #define IDRAM_BASE (0x80000000)
00123 #endif
00124 
00125 #define SDSP_CE0_BASE_REVBC   (0x00400000)
00126 #define SDSP_CE1_BASE_REVBC   (0x01400000)
00127 #define SDSP_IPRAM_BASE_REVBC (0x00000000)
00128     
00129 #define SDSP_CE2_BASE_REVBC   (0x02000000)
00130 #define SDSP_CE3_BASE_REVBC   (0x03000000)
00131 #define SDSP_IDRAM_BASE_REVBC (0x80000000)
00132 
00133 #define SDSP_CE0_BASE_REVE    (0x80000000)
00134 #define SDSP_CE1_BASE_REVE    (0x90000000)
00135 #define SDSP_IPRAM_BASE_REVE  (0x00000000)
00136     
00137 #define SDSP_CE2_BASE_REVE    (0xa0000000)
00138 #define SDSP_CE3_BASE_REVE    (0xb0000000)
00139 #define SDSP_IDRAM_BASE_REVE  ((SDSP_IPRAM_BASE_REVE) +(SDSP_IPRAM_SZ_REVE))
00140 
00141 #if defined(I_AM_SLAVE_DSP)
00142     #if (defined(REV_B)||defined(REV_C))
00143         #define CE0_BASE   (SDSP_CE0_BASE_REVBC)
00144         #define CE1_BASE   (SDSP_CE1_BASE_REVBC)
00145         #define IPRAM_BASE (SDSP_IPRAM_BASE_REVBC)
00146         
00147         #define CE2_BASE   (SDSP_CE2_BASE_REVBC)
00148         #define CE3_BASE   (SDSP_CE3_BASE_REVBC)
00149         #define IDRAM_BASE (SDSP_IDRAM_BASE_REVBC)
00150     #elif defined(REV_E)
00151         #define CE0_BASE   (SDSP_CE0_BASE_REVE)
00152         #define CE1_BASE   (SDSP_CE1_BASE_REVE)
00153         #define IPRAM_BASE (SDSP_IPRAM_BASE_REVE)
00154         #define SRAM_BASE  (0x00000000)
00155         
00156         #define CE2_BASE   (SDSP_CE2_BASE_REVE)
00157         #define CE3_BASE   (SDSP_CE3_BASE_REVE)
00158         #define IDRAM_BASE (SDSP_IDRAM_BASE_REVE)
00159     #endif
00160 #endif
00161 
00162 /* SDRAM: EVM has 2 4MB SDRAMs at CE2 and CE3; ROD has 16 MB SDRAM at CE2
00163    + another 16M at CE3 for 6701s */
00164 #ifdef TI_EVM
00165     #define SDRAM0_BASE  (CE2_BASE)
00166     #define SDRAM1_BASE  (CE3_BASE)
00167 
00168 #else
00169     #if (defined(I_AM_MASTER_DSP) || defined(I_AM_HOST))
00170         #define SDRAM0_BASE  (CE2_BASE)
00171         #define SDRAM1_BASE  ((CE2_BASE) + (SDRAM0_SZ))
00172     #endif
00173 
00174     #define SDSP_SDRAM0_BASE_REVBC  (SDSP_CE2_BASE_REVBC)
00175     #define SDSP_SDRAM1_BASE_REVBC  (SDSP_CE3_BASE_REVBC)
00176     #define SDSP_SDRAM0_BASE_REVE   (SDSP_CE2_BASE_REVE)
00177     #define SDSP_SDRAM1_BASE_REVE   (SDSP_CE3_BASE_REVE)
00178 
00179     #if defined(I_AM_SLAVE_DSP)
00180         #if (defined(REV_B)||defined(REV_C))
00181             #define SDRAM0_BASE  (SDSP_SDRAM0_BASE_REVBC)
00182             #define SDRAM1_BASE  (SDSP_SDRAM1_BASE_REVBC)
00183         #elif defined(REV_E)
00184             #define SDRAM0_BASE  (SDSP_SDRAM0_BASE_REVE)
00185             #define SDRAM1_BASE  (SDSP_SDRAM1_BASE_REVE)
00186         #endif
00187     #endif
00188 #endif
00189 
00190 /* The master DSP has a boot ROM at CE1; slaves each have a router FIFO */
00191 #ifndef TI_EVM
00192     #if (defined(I_AM_MASTER_DSP) || defined(I_AM_HOST))
00193         #define BOOT_ROM_BASE   (CE1_BASE)
00194         #define BOOT_ROM_SZ     (0x80000)      /* boot ROM is 512K */
00195 
00196     #elif (defined(I_AM_SLAVE_DSP))
00197         #define ROUTER_FIFO_BASE   (CE1_BASE)
00198         #define ROUTER_FIFO_SZ     (0x1000)      /* 1K words */
00199     #endif
00200 #endif
00201 
00202 /*************************************************************************************
00203  *                   Sizes of the available memories.
00204  ************************************************************************************/
00205 #if (defined(I_AM_MASTER_DSP)||defined(I_AM_HOST))
00206     /* 64KB of internal program memory and 64KB of internal data memory */
00207     #define IPRAM_SZ       (0x10000)
00208     #define IDRAM_SZ       (0x10000)
00209     #define CE1_SZ         (0x80000)
00210 #endif
00211 
00212 #define SDSP_IPRAM_SZ_REVBC   (0x10000)
00213 #define SDSP_IDRAM_SZ_REVBC   (0x10000)
00214 
00215 #define SDSP_IPRAM_SZ_REVE    (0x10000)
00216 #define SDSP_IDRAM_SZ_REVE    (0x10000)
00217 
00218 #if defined(I_AM_SLAVE_DSP)
00219     #if (defined(REV_B)||defined(REV_C))
00220         #define IPRAM_SZ  (SDSP_IPRAM_SZ_REVBC)
00221         #define IDRAM_SZ  (SDSP_IDRAM_SZ_REVBC)
00222     #elif defined(REV_E)
00223         #define IPRAM_SZ  (SDSP_IPRAM_SZ_REVE)
00224         #define IDRAM_SZ  (SDSP_IDRAM_SZ_REVE)
00225     #endif
00226 #endif
00227 
00228 #if (defined(I_AM_SLAVE_DSP)&&defined(REV_E))
00229     #define SRAM_SZ_NO_CACHE        (0x40000)
00230     #define SRAM_SZ_16K_CACHE       (0x3c000)
00231     #define SRAM_SZ_32K_CACHE       (0x38000)
00232     #define SRAM_SZ_48K_CACHE       (0x34000)
00233     #define SRAM_SZ_64K_CACHE       (0x30000)
00234 #endif
00235 
00236 #ifdef TI_EVM
00237     #define SDRAM0_SZ  (0x400000)
00238     #define SDRAM1_SZ  (0x400000)
00239 
00240 #else                             
00241     #if (defined(I_AM_MASTER_DSP) || defined(I_AM_HOST))
00242         /* 16 MB of SDRAM available on the ROD divided into two halves both on CE2 */
00243         #define SDRAM0_SZ  (0x800000)
00244         #define SDRAM1_SZ  (0x800000)
00245     #endif
00246 
00247     /* Rev. B & C: 16 MB of SDRAM on CE2 & CE3. Rev. E: 128 MB SDRAM. */
00248     #define SDSP_SDRAM_SZ_REVBC  0x01000000
00249     #define SDSP_SDRAM_SZ_REVE   0x08000000
00250 
00251     #if defined(I_AM_SLAVE_DSP)
00252         #if (defined(REV_B)||defined(REV_C))
00253             #define SDRAM0_SZ  (SDSP_SDRAM_SZ_REVBC)
00254             #define SDRAM1_SZ  (SDSP_SDRAM_SZ_REVBC)
00255         #elif defined(REV_E)
00256             #define SDRAM0_SZ  (SDSP_SDRAM_SZ_REVE)
00257             #define SDRAM1_SZ  (SDSP_SDRAM_SZ_REVE)
00258         #endif
00259     #endif
00260 #endif
00261 
00262 /************************************************************************************
00263  *                                IDRAM items
00264  ************************************************************************************
00265  * IDREGS_SZ bytes of IDRAM are reserved for communications registers.
00266  *
00267  * IDATA_SZ  bytes are reserved for important variables for which it's desirable they
00268  *           be kept (for monitoring) in a fixed location. Note that this method has a
00269  *   minor drawback in that the variables become 'far' data objects. To access them
00270  *   they must be declared "extern far", and the access will be slightly slower.
00271  *
00272  * IDRAM_MEM_SZ bytes are reserved for the linker to place general heap, stack and 
00273  *              'near' data objects (arrays and structures which are not declared
00274  *              'far').
00275  *
00276  * BURST_SZ bytes of IDRAM are reserved for the program to store data for immediate
00277  *          use. On the slaves it is a temporary store for data retrieved from the
00278  *   router FPGA via DMA.  This data typically is processed and added to histograms
00279  *   being accumulated in the SDRAM.  On the master it typically is a temporary store
00280  *   for data being transmitted to the front end electronics.
00281  *
00282  * **** THESE SIZES MUST BE THE SAME AS THE LENGTH PARAMETER OF THE CORRESPONDING
00283  *      MEMORY SECTION IN THE LINKER COMMAND FILE ****
00284  *
00285  * NOTE: If the memory section sizes are mistaken, the error will sometimes be caught
00286  *       by the compiler at compile time. Another check is done at run time inside
00287  *   checkMemBounds.c. Most larger data objects like the primitive buffers, text
00288  *   buffers, and external burst buffers do not have variables and memory segments
00289  *   declared for them; for these the space is 'virtually' allocated here and checked
00290  *   in chekMemBounds.c
00291  *
00292  */
00293 #if (defined(I_AM_MASTER_DSP) || defined(I_AM_HOST))
00294     #define IDREGS_SZ      (0x0080)
00295     #define IDATA_SZ       (0x0800)
00296     #define IDRAM_MEM_SZ   (0x7780)
00297     #define BURST_SZ       (0x8000) 
00298 #endif
00299 
00300 #define SDSP_IDREGS_SZ      (0x0080)
00301 #define SDSP_IDATA_SZ       (0x0800)
00302 #define SDSP_IDRAM_MEM_SZ   (0x7780)
00303 #define SDSP_BURST_SZ_REVBC (0x8000) 
00304 #define SDSP_BURST_SZ_REVE  (0x8000) 
00305 
00306 #if defined(I_AM_SLAVE_DSP)
00307     #define IDREGS_SZ      (SDSP_IDREGS_SZ)
00308     #define IDATA_SZ       (SDSP_IDATA_SZ)
00309     #define IDRAM_MEM_SZ   (SDSP_IDRAM_MEM_SZ)
00310 
00311     #if (defined(REV_B)||defined(REV_C))
00312         #define BURST_SZ  (SDSP_BURST_SZ_REVBC)
00313     #elif defined(REV_E)
00314         #define BURST_SZ  (SDSP_BURST_SZ_REVE)
00315     #endif
00316 #endif
00317 
00318 //dpsf: Temp fix to allow memoryPartitions.h to be used in conjunction with new comRegDfns.h:
00319 //dpsf: (comRegDfns.h defines memoryMap reg location & also contains IDREGS_BASE for host so
00320 //dpsf:  that it can look up the map register. memoryPartitions.h is now private to DSPs &
00321 //dpsf:  the map is the public interface.)
00322 #if ((defined(I_AM_MASTER_DSP))||(defined(I_AM_SLAVE_DSP)))
00323 #define IDREGS_BASE     (IDRAM_BASE)
00324 #define IDATA_BASE      ((IDREGS_BASE) + (IDREGS_SZ))
00325 /* IDRAM_BASE is kept for the physical memory base:   */
00326 #define IDRAM_MEM_BASE  ((IDATA_BASE)  + (IDATA_SZ))
00327 #define BURST_BFR_BASE   ((IDRAM_MEM_BASE) + (IDRAM_MEM_SZ))
00328 
00329 #define IDRAM_ALLOCATED ((IDREGS_SZ)+(IDATA_SZ)+(IDRAM_MEM_SZ)+(BURST_SZ))
00330 #endif
00331 /************************************************************************************
00332  *                                SDRAM0 items
00333  ************************************************************************************
00334  *** THIS MUST BE THE SAME AS THE LENGTH PARAMETER OF MEMORY SECTION XPROG IN
00335  *   THE LINKER COMMAND FILE. *****/
00336 #if (defined(I_AM_MASTER_DSP) || defined(I_AM_HOST))
00337     #define XPROG_SZ   (0x40000)
00338 #endif
00339 
00340 #define SDSP_XPROG_SZ (0x40000)
00341 
00342 #if defined(I_AM_SLAVE_DSP)
00343     #define XPROG_SZ  (SDSP_XPROG_SZ)
00344 #endif
00345 
00346 /* The ERR, INFO, DIAG and XFER buffers are the text buffers for sending messages
00347  * upstream to the host processor.  Slave text buffers are communicated to the host
00348  * via the master XFER buffer.  The XFER buffer is not used on the slaves.
00349  * The HOST_PRM and HOST_REP buffers are for primitive lists from the host and the
00350  * associated reply data.  Host to slave primitive and associated reply data are
00351  * transferred via the master DSP. The inter-DSP transfer buffers are small buffers
00352  * used for sending simple primitive lists from DSP to DSP (master to slave and
00353  * vice-versa). Note that in COMPACT mode the buffers are actually in IDRAM. */
00354 
00355 #define TXT_BFR_SZ           (0x8000)
00356 #define INTR_DSP_PRM_BFR_SZ  (0x800)
00357 #define INTR_DSP_REP_BFR_SZ  (0x800)
00358 
00359 #if (defined(I_AM_MASTER_DSP) || defined(I_AM_HOST))
00360     #define MDSP_PRM_BFR_SZ  (0x50000)
00361     #define MDSP_REP_BFR_SZ  (0x50000)
00362 #endif
00363 #define SDSP_PRM_BFR_SZ  (0x20000)
00364 #define SDSP_REP_BFR_SZ  (0x20000)
00365 
00366 
00367 #if (   (defined(I_AM_MASTER_DSP)) || (defined(I_AM_HOST)) \
00368      || (defined(I_AM_SLAVE_DSP)&&(defined(REV_B)||defined(REV_C)))  )
00369     #define ERR_BFR_BASE       ((SDRAM0_BASE) + (XPROG_SZ))
00370     #define INFO_BFR_BASE      ((ERR_BFR_BASE)  + (TXT_BFR_SZ))
00371     #define DIAG_BFR_BASE      ((INFO_BFR_BASE) + (TXT_BFR_SZ))
00372     #define XFER_BFR_BASE      ((DIAG_BFR_BASE) + (TXT_BFR_SZ))
00373     #define END_TEXT_BUFF      ((XFER_BFR_BASE) + (TXT_BFR_SZ))
00374 
00375     #define INTR_DSP_PRM_BFR_BASE_SND (END_TEXT_BUFF)
00376     #define INTR_DSP_REP_BFR_BASE_SND ((INTR_DSP_PRM_BFR_BASE_SND)+(INTR_DSP_PRM_BFR_SZ))
00377     #define INTR_DSP_PRM_BFR_BASE_PRC ((INTR_DSP_REP_BFR_BASE_SND)+(INTR_DSP_REP_BFR_SZ))
00378     #define INTR_DSP_REP_BFR_BASE_PRC ((INTR_DSP_PRM_BFR_BASE_PRC)+(INTR_DSP_PRM_BFR_SZ))
00379     #define END_IDSP_BUFF             ((INTR_DSP_REP_BFR_BASE_PRC)+(INTR_DSP_PRM_BFR_SZ))
00380 
00381     #define FREEMEM0_BASE (END_IDSP_BUFF)
00382     #define FREEMEM0_SZ   0x0000
00383 
00384 #elif (defined(I_AM_SLAVE_DSP)&&defined(REV_E))
00385     #define ERR_BFR_BASE       ((SDRAM0_BASE) + (XPROG_SZ))
00386     #define INFO_BFR_BASE      ((ERR_BFR_BASE)  + (TXT_BFR_SZ))
00387     #define DIAG_BFR_BASE      ((INFO_BFR_BASE) + (TXT_BFR_SZ))
00388     #define XFER_BFR_BASE      ((DIAG_BFR_BASE) + (TXT_BFR_SZ))
00389     #define END_TEXT_BUFF      ((XFER_BFR_BASE) + (TXT_BFR_SZ))
00390 
00391     #define INTR_DSP_PRM_BFR_BASE_SND (END_TEXT_BUFF)
00392     #define INTR_DSP_REP_BFR_BASE_SND ((INTR_DSP_PRM_BFR_BASE_SND)+(INTR_DSP_PRM_BFR_SZ))
00393     #define INTR_DSP_PRM_BFR_BASE_PRC ((INTR_DSP_REP_BFR_BASE_SND)+(INTR_DSP_REP_BFR_SZ))
00394     #define INTR_DSP_REP_BFR_BASE_PRC ((INTR_DSP_PRM_BFR_BASE_PRC)+(INTR_DSP_PRM_BFR_SZ))
00395     #define END_IDSP_BUFF             ((INTR_DSP_REP_BFR_BASE_PRC)+(INTR_DSP_PRM_BFR_SZ))
00396 
00397     #define FREEMEM0_BASE (END_IDSP_BUFF)
00398     #define FREEMEM0_SZ   0x0000
00399 #endif
00400 
00401 #if (defined(I_AM_MASTER_DSP) || defined(I_AM_HOST))
00402     #define MDSP_PRM_BFR_BASE  ((FREEMEM0_BASE) + (FREEMEM0_SZ))
00403     #define MDSP_REP_BFR_BASE  ((MDSP_PRM_BFR_BASE) + (MDSP_PRM_BFR_SZ)) 
00404     #define CMD_BUFFER_BASE    ((MDSP_REP_BFR_BASE) + (MDSP_REP_BFR_SZ))
00405     #define CMD_BUFFER_SZ      0x8000
00406     #define SDRAM0_FREE_BASE   ((CMD_BUFFER_BASE) +(CMD_BUFFER_SZ))
00407 #endif
00408 
00409 #define SDSP_PRM_BFR_BASE  ((FREEMEM0_BASE) + (FREEMEM0_SZ))
00410 #define SDSP_REP_BFR_BASE  ((SDSP_PRM_BFR_BASE) + (SDSP_PRM_BFR_SZ)) 
00411 
00412 #if (defined(I_AM_SLAVE_DSP))
00413     #define XBURST_BFR_BASE           ((SDSP_REP_BFR_BASE)+(SDSP_REP_BFR_SZ))
00414     #define XBURST_BFR_SZ             (0x38000) 
00415     
00416     #define BURST_BFR_RESERVED_BASE ((XBURST_BFR_BASE) +(XBURST_BFR_SZ))
00417     #define BURST_BFR_RESERVED_SZ   (0x8000)
00418     
00419     #define HISTOGRAM_DEFAULT_BASE  ((BURST_BFR_RESERVED_BASE) +(BURST_BFR_RESERVED_SZ))
00420     #define HISTOGRAM_DEFAULT_BASE_1 (CE3_BASE)
00421 
00422     #if (defined(REV_B) || defined(REV_C))
00423         #define FIT_DEFAULT_BASE  0x03c00000  //4 MB before memory top.
00424     #elif (defined(REV_E))
00425         #define FIT_DEFAULT_BASE  0xb7400000  //4 MB before memory top.
00426     #endif
00427 #endif
00428 
00429 #if   defined(I_AM_MASTER_DSP)
00430     #define SDRAM0_ALLOCATED ((SDRAM0_FREE_BASE) -(SDRAM0_BASE))
00431 #elif defined(I_AM_SLAVE_DSP)
00432     #define SDRAM0_ALLOCATED ((HISTOGRAM_DEFAULT_BASE) -(SDRAM0_BASE))
00433 #endif
00434 
00435 #define MODULE_DATA_BASE    0x02400000
00436 #if   defined(SCT_ROD)
00437     #define MODULE_DATA_SZ      0x00080000      /* .5 MB */
00438 #elif defined(PIXEL_ROD)
00439     #define MODULE_DATA_SZ      0x00b00000      /* 11 MB */
00440 #endif
00441 
00442 
00443 /* default position for trapped events is in high memory: whereas the burst buffers
00444    are always needed for trapping events, this is potentially reserved memory for
00445    gathering trapped events; it is intended to be a suggestion when running the event
00446    trapping task. */
00447 #if  (defined(I_AM_MASTER_DSP) || defined(I_AM_HOST))
00448     #define SLV_SDRAM1_BASE          (0x03000000)
00449     #define SLV_SDRAM1_SZ            (0x01000000)   /* needed by VME host */
00450     #define EVENT_TRAP_DEFAULT_SZ    (0x20000)
00451     #define EVENT_TRAP_DEFAULT_BASE  ((SLV_SDRAM1_BASE) +(SLV_SDRAM1_SZ) \
00452                                       -(EVENT_TRAP_DEFAULT_SZ))
00453 #else
00454     #define EVENT_TRAP_DEFAULT_SZ    (0x20000)
00455     #define EVENT_TRAP_DEFAULT_BASE  ((SDRAM1_BASE) +(SDRAM1_SZ) \
00456                                       -(EVENT_TRAP_DEFAULT_SZ))
00457 #endif
00458 
00459 /* SDRAM1: Free space for application defined data on SCT RODs; for Pixel RODs
00460            the module database takes up the last 4 MB of SDRAM0 & the first 7
00461            MB of SDRAM1 (see above) & the upper 1 MB is free space. (this is
00462            handled by memory sections now). */
00463 
00464 #define SDRAM1_FREE_BASE   (SDRAM1_BASE)
00465 #define SDRAM1_ALLOCATED   0
00466 
00467 #if defined(TI_EVM)  /* need a histogram base for SDRAM1 */
00468     #define HISTOGRAM_BASE1   ((SDRAM1_BASE) +(0x40000))
00469 #endif
00470 
00471 /************************************************************************************
00472  *    Rod FPGA memory mapped items from CE0 (FPGA area simulated during simulation):
00473  ************************************************************************************/
00474 #if (defined(I_AM_MASTER_DSP)|| defined(I_AM_HOST))
00475     /* base address for memory mapped registers and FIFOs */
00476     #define REG_BASE    (CE0_BASE)
00477 
00478     /* offsets into each device  These are FPGA-centric offsets, i.e. from the MDSP
00479        point of view they need to be left shifted 2 bits (words -> bytes). This is
00480        done where needed in the files containing the access routines. */
00481     #define FMT_BASE  (0x0)
00482     #define EFB_BASE  (0x800)
00483     #define RTR_BASE  (0x900)
00484     #define RCF_BASE  (0x1000)
00485     #define FIFO_BASE (0x1800)
00486     #define BOC_BASE  (0x2000)
00487     #define SDSP_BASE (0xE0000)
00488     
00489     #define LED_OFFSET 0x100
00490     #define HEARTBEAT_ADR ((UINT32 *)(((RCF_BASE + LED_OFFSET) << 2) + REG_BASE))
00491     
00492     /* If simulating the ROD, the SDSP communication registers and other memory
00493        sections must be simulated- these are put in some extra memory allocated
00494        by the GEL mapSet6201 function 1 MB above the FPGA register base (CE0). */
00495     #define SIM_SDSP_REG_BASE(sdsp)  (REG_BASE +0x100000 -0xa0*4 +0xa0*(sdsp))
00496     #define SIM_SDSP_IMEM_BASE(sdsp) (REG_BASE +0x100000  +0x40000*(sdsp))
00497     #define SIM_SDSP_XMEM0_BASE(sdsp) (REG_BASE +0x200000 +0x200000*(sdsp))
00498     //For items in high SDSP CE0 or CE1 memory. Note that these memories wrap.
00499     #define SIM_SDSP_XMEM1_BASE(sdsp) (REG_BASE +0xa00000 +0x100000*(sdsp))
00500 
00501 #elif defined(I_AM_SLAVE_DSP)
00502     #define ROUTER_FIFO_ADDR       (CE1_BASE)
00503 
00504 #endif
00505 
00506 #endif

Generated on Fri Dec 16 19:38:13 2005 for SCT DAQ/DCS Software - C++ by doxygen 1.3.5