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00073 #ifndef MEMORY_PARTITIONS
00074 #define MEMORY_PARTITIONS
00075
00076 #include "processor.h"
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00114
00115 #if ((defined(I_AM_MASTER_DSP))||(defined(I_AM_HOST)))
00116 #define CE0_BASE (0x00400000)
00117 #define CE1_BASE (0x01400000)
00118 #define IPRAM_BASE (0x00000000)
00119
00120 #define CE2_BASE (0x02000000)
00121 #define CE3_BASE (0x03000000)
00122 #define IDRAM_BASE (0x80000000)
00123 #endif
00124
00125 #define SDSP_CE0_BASE_REVBC (0x00400000)
00126 #define SDSP_CE1_BASE_REVBC (0x01400000)
00127 #define SDSP_IPRAM_BASE_REVBC (0x00000000)
00128
00129 #define SDSP_CE2_BASE_REVBC (0x02000000)
00130 #define SDSP_CE3_BASE_REVBC (0x03000000)
00131 #define SDSP_IDRAM_BASE_REVBC (0x80000000)
00132
00133 #define SDSP_CE0_BASE_REVE (0x80000000)
00134 #define SDSP_CE1_BASE_REVE (0x90000000)
00135 #define SDSP_IPRAM_BASE_REVE (0x00000000)
00136
00137 #define SDSP_CE2_BASE_REVE (0xa0000000)
00138 #define SDSP_CE3_BASE_REVE (0xb0000000)
00139 #define SDSP_IDRAM_BASE_REVE ((SDSP_IPRAM_BASE_REVE) +(SDSP_IPRAM_SZ_REVE))
00140
00141 #if defined(I_AM_SLAVE_DSP)
00142 #if (defined(REV_B)||defined(REV_C))
00143 #define CE0_BASE (SDSP_CE0_BASE_REVBC)
00144 #define CE1_BASE (SDSP_CE1_BASE_REVBC)
00145 #define IPRAM_BASE (SDSP_IPRAM_BASE_REVBC)
00146
00147 #define CE2_BASE (SDSP_CE2_BASE_REVBC)
00148 #define CE3_BASE (SDSP_CE3_BASE_REVBC)
00149 #define IDRAM_BASE (SDSP_IDRAM_BASE_REVBC)
00150 #elif defined(REV_E)
00151 #define CE0_BASE (SDSP_CE0_BASE_REVE)
00152 #define CE1_BASE (SDSP_CE1_BASE_REVE)
00153 #define IPRAM_BASE (SDSP_IPRAM_BASE_REVE)
00154 #define SRAM_BASE (0x00000000)
00155
00156 #define CE2_BASE (SDSP_CE2_BASE_REVE)
00157 #define CE3_BASE (SDSP_CE3_BASE_REVE)
00158 #define IDRAM_BASE (SDSP_IDRAM_BASE_REVE)
00159 #endif
00160 #endif
00161
00162
00163
00164 #ifdef TI_EVM
00165 #define SDRAM0_BASE (CE2_BASE)
00166 #define SDRAM1_BASE (CE3_BASE)
00167
00168 #else
00169 #if (defined(I_AM_MASTER_DSP) || defined(I_AM_HOST))
00170 #define SDRAM0_BASE (CE2_BASE)
00171 #define SDRAM1_BASE ((CE2_BASE) + (SDRAM0_SZ))
00172 #endif
00173
00174 #define SDSP_SDRAM0_BASE_REVBC (SDSP_CE2_BASE_REVBC)
00175 #define SDSP_SDRAM1_BASE_REVBC (SDSP_CE3_BASE_REVBC)
00176 #define SDSP_SDRAM0_BASE_REVE (SDSP_CE2_BASE_REVE)
00177 #define SDSP_SDRAM1_BASE_REVE (SDSP_CE3_BASE_REVE)
00178
00179 #if defined(I_AM_SLAVE_DSP)
00180 #if (defined(REV_B)||defined(REV_C))
00181 #define SDRAM0_BASE (SDSP_SDRAM0_BASE_REVBC)
00182 #define SDRAM1_BASE (SDSP_SDRAM1_BASE_REVBC)
00183 #elif defined(REV_E)
00184 #define SDRAM0_BASE (SDSP_SDRAM0_BASE_REVE)
00185 #define SDRAM1_BASE (SDSP_SDRAM1_BASE_REVE)
00186 #endif
00187 #endif
00188 #endif
00189
00190
00191 #ifndef TI_EVM
00192 #if (defined(I_AM_MASTER_DSP) || defined(I_AM_HOST))
00193 #define BOOT_ROM_BASE (CE1_BASE)
00194 #define BOOT_ROM_SZ (0x80000)
00195
00196 #elif (defined(I_AM_SLAVE_DSP))
00197 #define ROUTER_FIFO_BASE (CE1_BASE)
00198 #define ROUTER_FIFO_SZ (0x1000)
00199 #endif
00200 #endif
00201
00202
00203
00204
00205 #if (defined(I_AM_MASTER_DSP)||defined(I_AM_HOST))
00206
00207 #define IPRAM_SZ (0x10000)
00208 #define IDRAM_SZ (0x10000)
00209 #define CE1_SZ (0x80000)
00210 #endif
00211
00212 #define SDSP_IPRAM_SZ_REVBC (0x10000)
00213 #define SDSP_IDRAM_SZ_REVBC (0x10000)
00214
00215 #define SDSP_IPRAM_SZ_REVE (0x10000)
00216 #define SDSP_IDRAM_SZ_REVE (0x10000)
00217
00218 #if defined(I_AM_SLAVE_DSP)
00219 #if (defined(REV_B)||defined(REV_C))
00220 #define IPRAM_SZ (SDSP_IPRAM_SZ_REVBC)
00221 #define IDRAM_SZ (SDSP_IDRAM_SZ_REVBC)
00222 #elif defined(REV_E)
00223 #define IPRAM_SZ (SDSP_IPRAM_SZ_REVE)
00224 #define IDRAM_SZ (SDSP_IDRAM_SZ_REVE)
00225 #endif
00226 #endif
00227
00228 #if (defined(I_AM_SLAVE_DSP)&&defined(REV_E))
00229 #define SRAM_SZ_NO_CACHE (0x40000)
00230 #define SRAM_SZ_16K_CACHE (0x3c000)
00231 #define SRAM_SZ_32K_CACHE (0x38000)
00232 #define SRAM_SZ_48K_CACHE (0x34000)
00233 #define SRAM_SZ_64K_CACHE (0x30000)
00234 #endif
00235
00236 #ifdef TI_EVM
00237 #define SDRAM0_SZ (0x400000)
00238 #define SDRAM1_SZ (0x400000)
00239
00240 #else
00241 #if (defined(I_AM_MASTER_DSP) || defined(I_AM_HOST))
00242
00243 #define SDRAM0_SZ (0x800000)
00244 #define SDRAM1_SZ (0x800000)
00245 #endif
00246
00247
00248 #define SDSP_SDRAM_SZ_REVBC 0x01000000
00249 #define SDSP_SDRAM_SZ_REVE 0x08000000
00250
00251 #if defined(I_AM_SLAVE_DSP)
00252 #if (defined(REV_B)||defined(REV_C))
00253 #define SDRAM0_SZ (SDSP_SDRAM_SZ_REVBC)
00254 #define SDRAM1_SZ (SDSP_SDRAM_SZ_REVBC)
00255 #elif defined(REV_E)
00256 #define SDRAM0_SZ (SDSP_SDRAM_SZ_REVE)
00257 #define SDRAM1_SZ (SDSP_SDRAM_SZ_REVE)
00258 #endif
00259 #endif
00260 #endif
00261
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00292
00293 #if (defined(I_AM_MASTER_DSP) || defined(I_AM_HOST))
00294 #define IDREGS_SZ (0x0080)
00295 #define IDATA_SZ (0x0800)
00296 #define IDRAM_MEM_SZ (0x7780)
00297 #define BURST_SZ (0x8000)
00298 #endif
00299
00300 #define SDSP_IDREGS_SZ (0x0080)
00301 #define SDSP_IDATA_SZ (0x0800)
00302 #define SDSP_IDRAM_MEM_SZ (0x7780)
00303 #define SDSP_BURST_SZ_REVBC (0x8000)
00304 #define SDSP_BURST_SZ_REVE (0x8000)
00305
00306 #if defined(I_AM_SLAVE_DSP)
00307 #define IDREGS_SZ (SDSP_IDREGS_SZ)
00308 #define IDATA_SZ (SDSP_IDATA_SZ)
00309 #define IDRAM_MEM_SZ (SDSP_IDRAM_MEM_SZ)
00310
00311 #if (defined(REV_B)||defined(REV_C))
00312 #define BURST_SZ (SDSP_BURST_SZ_REVBC)
00313 #elif defined(REV_E)
00314 #define BURST_SZ (SDSP_BURST_SZ_REVE)
00315 #endif
00316 #endif
00317
00318
00319
00320
00321
00322 #if ((defined(I_AM_MASTER_DSP))||(defined(I_AM_SLAVE_DSP)))
00323 #define IDREGS_BASE (IDRAM_BASE)
00324 #define IDATA_BASE ((IDREGS_BASE) + (IDREGS_SZ))
00325
00326 #define IDRAM_MEM_BASE ((IDATA_BASE) + (IDATA_SZ))
00327 #define BURST_BFR_BASE ((IDRAM_MEM_BASE) + (IDRAM_MEM_SZ))
00328
00329 #define IDRAM_ALLOCATED ((IDREGS_SZ)+(IDATA_SZ)+(IDRAM_MEM_SZ)+(BURST_SZ))
00330 #endif
00331
00332
00333
00334
00335
00336 #if (defined(I_AM_MASTER_DSP) || defined(I_AM_HOST))
00337 #define XPROG_SZ (0x40000)
00338 #endif
00339
00340 #define SDSP_XPROG_SZ (0x40000)
00341
00342 #if defined(I_AM_SLAVE_DSP)
00343 #define XPROG_SZ (SDSP_XPROG_SZ)
00344 #endif
00345
00346
00347
00348
00349
00350
00351
00352
00353
00354
00355 #define TXT_BFR_SZ (0x8000)
00356 #define INTR_DSP_PRM_BFR_SZ (0x800)
00357 #define INTR_DSP_REP_BFR_SZ (0x800)
00358
00359 #if (defined(I_AM_MASTER_DSP) || defined(I_AM_HOST))
00360 #define MDSP_PRM_BFR_SZ (0x50000)
00361 #define MDSP_REP_BFR_SZ (0x50000)
00362 #endif
00363 #define SDSP_PRM_BFR_SZ (0x20000)
00364 #define SDSP_REP_BFR_SZ (0x20000)
00365
00366
00367 #if ( (defined(I_AM_MASTER_DSP)) || (defined(I_AM_HOST)) \
00368 || (defined(I_AM_SLAVE_DSP)&&(defined(REV_B)||defined(REV_C))) )
00369 #define ERR_BFR_BASE ((SDRAM0_BASE) + (XPROG_SZ))
00370 #define INFO_BFR_BASE ((ERR_BFR_BASE) + (TXT_BFR_SZ))
00371 #define DIAG_BFR_BASE ((INFO_BFR_BASE) + (TXT_BFR_SZ))
00372 #define XFER_BFR_BASE ((DIAG_BFR_BASE) + (TXT_BFR_SZ))
00373 #define END_TEXT_BUFF ((XFER_BFR_BASE) + (TXT_BFR_SZ))
00374
00375 #define INTR_DSP_PRM_BFR_BASE_SND (END_TEXT_BUFF)
00376 #define INTR_DSP_REP_BFR_BASE_SND ((INTR_DSP_PRM_BFR_BASE_SND)+(INTR_DSP_PRM_BFR_SZ))
00377 #define INTR_DSP_PRM_BFR_BASE_PRC ((INTR_DSP_REP_BFR_BASE_SND)+(INTR_DSP_REP_BFR_SZ))
00378 #define INTR_DSP_REP_BFR_BASE_PRC ((INTR_DSP_PRM_BFR_BASE_PRC)+(INTR_DSP_PRM_BFR_SZ))
00379 #define END_IDSP_BUFF ((INTR_DSP_REP_BFR_BASE_PRC)+(INTR_DSP_PRM_BFR_SZ))
00380
00381 #define FREEMEM0_BASE (END_IDSP_BUFF)
00382 #define FREEMEM0_SZ 0x0000
00383
00384 #elif (defined(I_AM_SLAVE_DSP)&&defined(REV_E))
00385 #define ERR_BFR_BASE ((SDRAM0_BASE) + (XPROG_SZ))
00386 #define INFO_BFR_BASE ((ERR_BFR_BASE) + (TXT_BFR_SZ))
00387 #define DIAG_BFR_BASE ((INFO_BFR_BASE) + (TXT_BFR_SZ))
00388 #define XFER_BFR_BASE ((DIAG_BFR_BASE) + (TXT_BFR_SZ))
00389 #define END_TEXT_BUFF ((XFER_BFR_BASE) + (TXT_BFR_SZ))
00390
00391 #define INTR_DSP_PRM_BFR_BASE_SND (END_TEXT_BUFF)
00392 #define INTR_DSP_REP_BFR_BASE_SND ((INTR_DSP_PRM_BFR_BASE_SND)+(INTR_DSP_PRM_BFR_SZ))
00393 #define INTR_DSP_PRM_BFR_BASE_PRC ((INTR_DSP_REP_BFR_BASE_SND)+(INTR_DSP_REP_BFR_SZ))
00394 #define INTR_DSP_REP_BFR_BASE_PRC ((INTR_DSP_PRM_BFR_BASE_PRC)+(INTR_DSP_PRM_BFR_SZ))
00395 #define END_IDSP_BUFF ((INTR_DSP_REP_BFR_BASE_PRC)+(INTR_DSP_PRM_BFR_SZ))
00396
00397 #define FREEMEM0_BASE (END_IDSP_BUFF)
00398 #define FREEMEM0_SZ 0x0000
00399 #endif
00400
00401 #if (defined(I_AM_MASTER_DSP) || defined(I_AM_HOST))
00402 #define MDSP_PRM_BFR_BASE ((FREEMEM0_BASE) + (FREEMEM0_SZ))
00403 #define MDSP_REP_BFR_BASE ((MDSP_PRM_BFR_BASE) + (MDSP_PRM_BFR_SZ))
00404 #define CMD_BUFFER_BASE ((MDSP_REP_BFR_BASE) + (MDSP_REP_BFR_SZ))
00405 #define CMD_BUFFER_SZ 0x8000
00406 #define SDRAM0_FREE_BASE ((CMD_BUFFER_BASE) +(CMD_BUFFER_SZ))
00407 #endif
00408
00409 #define SDSP_PRM_BFR_BASE ((FREEMEM0_BASE) + (FREEMEM0_SZ))
00410 #define SDSP_REP_BFR_BASE ((SDSP_PRM_BFR_BASE) + (SDSP_PRM_BFR_SZ))
00411
00412 #if (defined(I_AM_SLAVE_DSP))
00413 #define XBURST_BFR_BASE ((SDSP_REP_BFR_BASE)+(SDSP_REP_BFR_SZ))
00414 #define XBURST_BFR_SZ (0x38000)
00415
00416 #define BURST_BFR_RESERVED_BASE ((XBURST_BFR_BASE) +(XBURST_BFR_SZ))
00417 #define BURST_BFR_RESERVED_SZ (0x8000)
00418
00419 #define HISTOGRAM_DEFAULT_BASE ((BURST_BFR_RESERVED_BASE) +(BURST_BFR_RESERVED_SZ))
00420 #define HISTOGRAM_DEFAULT_BASE_1 (CE3_BASE)
00421
00422 #if (defined(REV_B) || defined(REV_C))
00423 #define FIT_DEFAULT_BASE 0x03c00000 //4 MB before memory top.
00424 #elif (defined(REV_E))
00425 #define FIT_DEFAULT_BASE 0xb7400000 //4 MB before memory top.
00426 #endif
00427 #endif
00428
00429 #if defined(I_AM_MASTER_DSP)
00430 #define SDRAM0_ALLOCATED ((SDRAM0_FREE_BASE) -(SDRAM0_BASE))
00431 #elif defined(I_AM_SLAVE_DSP)
00432 #define SDRAM0_ALLOCATED ((HISTOGRAM_DEFAULT_BASE) -(SDRAM0_BASE))
00433 #endif
00434
00435 #define MODULE_DATA_BASE 0x02400000
00436 #if defined(SCT_ROD)
00437 #define MODULE_DATA_SZ 0x00080000
00438 #elif defined(PIXEL_ROD)
00439 #define MODULE_DATA_SZ 0x00b00000
00440 #endif
00441
00442
00443
00444
00445
00446
00447 #if (defined(I_AM_MASTER_DSP) || defined(I_AM_HOST))
00448 #define SLV_SDRAM1_BASE (0x03000000)
00449 #define SLV_SDRAM1_SZ (0x01000000)
00450 #define EVENT_TRAP_DEFAULT_SZ (0x20000)
00451 #define EVENT_TRAP_DEFAULT_BASE ((SLV_SDRAM1_BASE) +(SLV_SDRAM1_SZ) \
00452 -(EVENT_TRAP_DEFAULT_SZ))
00453 #else
00454 #define EVENT_TRAP_DEFAULT_SZ (0x20000)
00455 #define EVENT_TRAP_DEFAULT_BASE ((SDRAM1_BASE) +(SDRAM1_SZ) \
00456 -(EVENT_TRAP_DEFAULT_SZ))
00457 #endif
00458
00459
00460
00461
00462
00463
00464 #define SDRAM1_FREE_BASE (SDRAM1_BASE)
00465 #define SDRAM1_ALLOCATED 0
00466
00467 #if defined(TI_EVM)
00468 #define HISTOGRAM_BASE1 ((SDRAM1_BASE) +(0x40000))
00469 #endif
00470
00471
00472
00473
00474 #if (defined(I_AM_MASTER_DSP)|| defined(I_AM_HOST))
00475
00476 #define REG_BASE (CE0_BASE)
00477
00478
00479
00480
00481 #define FMT_BASE (0x0)
00482 #define EFB_BASE (0x800)
00483 #define RTR_BASE (0x900)
00484 #define RCF_BASE (0x1000)
00485 #define FIFO_BASE (0x1800)
00486 #define BOC_BASE (0x2000)
00487 #define SDSP_BASE (0xE0000)
00488
00489 #define LED_OFFSET 0x100
00490 #define HEARTBEAT_ADR ((UINT32 *)(((RCF_BASE + LED_OFFSET) << 2) + REG_BASE))
00491
00492
00493
00494
00495 #define SIM_SDSP_REG_BASE(sdsp) (REG_BASE +0x100000 -0xa0*4 +0xa0*(sdsp))
00496 #define SIM_SDSP_IMEM_BASE(sdsp) (REG_BASE +0x100000 +0x40000*(sdsp))
00497 #define SIM_SDSP_XMEM0_BASE(sdsp) (REG_BASE +0x200000 +0x200000*(sdsp))
00498
00499 #define SIM_SDSP_XMEM1_BASE(sdsp) (REG_BASE +0xa00000 +0x100000*(sdsp))
00500
00501 #elif defined(I_AM_SLAVE_DSP)
00502 #define ROUTER_FIFO_ADDR (CE1_BASE)
00503
00504 #endif
00505
00506 #endif