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macros.h

00001 /************************************************************************************
00002  * macros.h
00003  *                            
00004  *  synopsis: Contains most macro (text-replacement) definitions. Code segments are
00005  *            converted into macros if they are 1) repetitive in nature or 2) devoted
00006  *     to a single class of functionality, and taking them out of the function code
00007  *     enhances readability (less cluttered code).  The macros' functions must either
00008  *     not be critical to other code in the function, or easily comprehensible via
00009  *     the macro name.
00010  *
00011  *  Douglas Ferguson, UW Madison/LBNL   (510) 486-5230           dpferguson@lbl.gov
00012  ************************************************************************************/
00013 #ifndef MACROS_H
00014 #define MACROS_H 
00015 
00016 #include "timing.h"
00017 
00018 /******************** Histogramming Error & Warning macros: *************************/
00019 #define histoVerboseAsmWarnM() {  \
00020     newInformation(__FILE__, __LINE__, \
00021        "histoSetup warning: verbose mode is not supported in assembly," \
00022        " flag will be ignored.\n"); \
00023 }
00024 
00025 #define histoFormatAsmFatalM() { \
00026     newError(&returnCode, ASM_FORMAT_ERROR, FATAL_ERR, "histoSetup", \
00027        "The full data format is a diagnostic mode supported in the c code only.\n", \
00028        __FILE__, __LINE__);  \
00029     return returnCode;       \
00030 }
00031 
00032 #define histoBinSizeAsmFatalM() { \
00033     newError(&returnCode, ASM_BINSIZE_ERROR, FATAL_ERR, "histoSetup", \
00034        "The selected bin size is not yet implemented in assembly code.\n", \
00035        __FILE__, __LINE__);  \
00036     return returnCode;       \
00037 }
00038 
00039 #define histoChipOccAsmFatalM() { \
00040     newError(&returnCode, ASM_CHIPOCC_ERROR, FATAL_ERR, "histoSetup", \
00041        "Chip occupancy histograms are not yet implemented in assembly code.\n", \
00042        __FILE__, __LINE__);  \
00043     return returnCode;       \
00044 }
00045 
00046 /******************************** Debugging Tools: **********************************/
00047 #if (defined(I_AM_MASTER_DSP))
00048 
00049 #elif (defined(I_AM_SLAVE_DSP))
00050 
00051 #define eventInfo0M {                                       \
00052     CSR&= ~1;                                               \
00053     genEventInfo->code=         0;                          \
00054     genEventInfo->loopCnt =     READ_REG(LOOP_REG);         \
00055     genEventInfo->timeStamp=    TIMER_getCount(timer1);     \
00056     genEventInfo->procTime=    0;                           \
00057                                                             \
00058     genEventInfo->trapStat[0]=  READ_REG(TRAPSTAT_REG1_0);  \
00059     genEventInfo->trapStat[1]=  READ_REG(TRAPSTAT_REG1_1);  \
00060     genEventInfo->trapStat[2]=  READ_REG(TRAPSTAT_REG1_2);  \
00061     genEventInfo->isrState=     evtMgrCtrl.isrState;        \
00062                                                             \
00063     genEventInfo->nEvents=      evtMgrCtrl.nEventsTot;      \
00064     genEventInfo->nHistoEvents= READ_REG(HSTAT_REG_1);      \
00065     genEventInfo->p4MaskStat=   MCBSP_FGET(PCR1, DXSTAT);   \
00066     genEventInfo->maskFlag=     evtMgrCtrl.pin4MaskDown;    \
00067                                                             \
00068     if ((++genEventInfo) >= ((GenEventInfo *) 0xb4000000))  \
00069         genEventInfo= (GenEventInfo *) 0xb0000100;          \
00070     genEventInfo->code = 0x0badcafe;                        \
00071     genEventInfoTail->badcafe_address = (&(genEventInfo->code)); \
00072     CSR|=  1;                                               \
00073 }
00074 
00075 #define eventInfo1M {                                       \
00076     CSR&= ~1;                                               \
00077     genEventInfo->code=         1;                          \
00078     genEventInfo->loopCnt =     READ_REG(LOOP_REG);         \
00079     genEventInfo->timeStamp=    TIMER_getCount(timer1);     \
00080     genEventInfo->procTime=     0;                          \
00081                                                             \
00082     genEventInfo->trapStat[0]=  READ_REG(TRAPSTAT_REG1_0);  \
00083     genEventInfo->trapStat[1]=  READ_REG(TRAPSTAT_REG1_1);  \
00084     genEventInfo->trapStat[2]=  READ_REG(TRAPSTAT_REG1_2);  \
00085     genEventInfo->isrState=     evtMgrCtrl.isrState;        \
00086                                                             \
00087     genEventInfo->nEvents=      evtMgrCtrl.nEventsTot;      \
00088     genEventInfo->nHistoEvents= READ_REG(HSTAT_REG_1);      \
00089     genEventInfo->p4MaskStat=   MCBSP_FGET(PCR1, DXSTAT);   \
00090     genEventInfo->maskFlag=     evtMgrCtrl.pin4MaskDown;    \
00091                                                             \
00092     if ((++genEventInfo) >= ((GenEventInfo *) 0xb4000000))  \
00093         genEventInfo= (GenEventInfo *) 0xb0000100;          \
00094     genEventInfo->code = 0x0badcafe;                        \
00095                                                             \
00096     genEventInfoTail->badcafe_address = (&(genEventInfo->code));\
00097                                                             \
00098     CSR|=  1;                                               \
00099 }
00100 
00101 #define eventInfo2M {                                       \
00102     CSR&= ~1;                                               \
00103     genEventInfo->code=         2;                          \
00104     genEventInfo->loopCnt =     READ_REG(LOOP_REG);         \
00105     genEventInfo->timeStamp=    TIMER_getCount(timer1);     \
00106     genEventInfo->procTime=     0;                          \
00107                                                             \
00108     genEventInfo->trapStat[0]=  READ_REG(TRAPSTAT_REG1_0);  \
00109     genEventInfo->trapStat[1]=  READ_REG(TRAPSTAT_REG1_1);  \
00110     genEventInfo->trapStat[2]=  READ_REG(TRAPSTAT_REG1_2);  \
00111     genEventInfo->isrState=     evtMgrCtrl.isrState;        \
00112                                                             \
00113     genEventInfo->nEvents=      evtMgrCtrl.nEventsTot;      \
00114     genEventInfo->nHistoEvents= READ_REG(HSTAT_REG_1);      \
00115     genEventInfo->p4MaskStat=   MCBSP_FGET(PCR1, DXSTAT);   \
00116     genEventInfo->maskFlag=     evtMgrCtrl.pin4MaskDown;    \
00117                                                             \
00118     if ((++genEventInfo) >= ((GenEventInfo *) 0xb4000000))  \
00119         genEventInfo= (GenEventInfo *) 0xb0000100;          \
00120     genEventInfo->code = 0x0badcafe;                        \
00121                                                             \
00122     genEventInfoTail->badcafe_address = (&(genEventInfo->code)); \
00123                                                             \
00124     CSR|=  1;                                               \
00125 }
00126 
00127 #define eventInfo3M {                                       \
00128     CSR&= ~1;                                               \
00129     genEventInfo->code=         3;                          \
00130     genEventInfo->loopCnt =     READ_REG(LOOP_REG);         \
00131     genEventInfo->timeStamp=    TIMER_getCount(timer1);     \
00132     genEventInfo->procTime=     procTime;                   \
00133                                                             \
00134     genEventInfo->trapStat[0]=  READ_REG(TRAPSTAT_REG1_0);  \
00135     genEventInfo->trapStat[1]=  READ_REG(TRAPSTAT_REG1_1);  \
00136     genEventInfo->trapStat[2]=  READ_REG(TRAPSTAT_REG1_2);  \
00137     genEventInfo->isrState=     evtMgrCtrl.isrState;        \
00138                                                             \
00139     genEventInfo->nEvents=      evtMgrCtrl.nEventsTot;      \
00140     genEventInfo->nHistoEvents= READ_REG(HSTAT_REG_1);      \
00141     genEventInfo->p4MaskStat=   MCBSP_FGET(PCR1, DXSTAT);   \
00142     genEventInfo->maskFlag=     evtMgrCtrl.pin4MaskDown;    \
00143                                                             \
00144     if ((++genEventInfo) >= ((GenEventInfo *) 0xb4000000))  \
00145         genEventInfo= (GenEventInfo *) 0xb0000100;          \
00146     genEventInfo->code = 0x0badcafe;                        \
00147                                                             \
00148     genEventInfoTail->badcafe_address = (&(genEventInfo->code)); \
00149                                                             \
00150     CSR|=  1;                                               \
00151 }
00152 
00153 //For the ISR, (**do NOT toggle GIE**):
00154 #define eventInfo4M {                                       \
00155     genEventInfo->code=         4;                          \
00156     genEventInfo->loopCnt =     READ_REG(LOOP_REG);         \
00157     genEventInfo->timeStamp=    TIMER_getCount(timer1);     \
00158     genEventInfo->procTime=     0;                          \
00159                                                             \
00160     genEventInfo->trapStat[0]=  READ_REG(TRAPSTAT_REG1_0);  \
00161     genEventInfo->trapStat[1]=  READ_REG(TRAPSTAT_REG1_1);  \
00162     genEventInfo->trapStat[2]=  READ_REG(TRAPSTAT_REG1_2);  \
00163     genEventInfo->isrState=     evtMgrCtrl.isrState;        \
00164                                                             \
00165     genEventInfo->nEvents=      evtMgrCtrl.nEventsTot;      \
00166     genEventInfo->nHistoEvents= READ_REG(HSTAT_REG_1);      \
00167     genEventInfo->p4MaskStat=   MCBSP_FGET(PCR1, DXSTAT);   \
00168     genEventInfo->maskFlag=     evtMgrCtrl.pin4MaskDown;    \
00169                                                             \
00170     if ((++genEventInfo) >= ((GenEventInfo *) 0xb4000000))  \
00171         genEventInfo= (GenEventInfo *) 0xb0000100;          \
00172     genEventInfo->code = 0x0badcafe;                        \
00173     genEventInfoTail->badcafe_address = (&(genEventInfo->code));\
00174                                                             \
00175     }
00176 
00177 #endif
00178 
00179 /********************************** Error Macros:  **********************************/
00180 /* macros to check for errors and call error handler routines */
00181 #define newErrFatalM(err, level, routine, msg) {                          \
00182     newError(&returnCode, err, level, routine, msg, __FILE__, __LINE__);  \
00183     if (FATAL(returnCode)) { return returnCode; }                         \
00184 }
00185 
00186 #define addErrFatalM(err, status, routine, subroutine) {                  \
00187     if (status != SUCCESS) {                                              \
00188         addError(err, status, routine, subroutine, __FILE__, __LINE__);   \
00189         if (FATAL(returnCode)) { return returnCode; }                     \
00190     }                                                                     \
00191 }
00192 
00193 #define newErrM(err, level, routine, msg) {                               \
00194     newError(&returnCode, err, level, routine, msg, __FILE__, __LINE__);  \
00195 }
00196 
00197 #define addErrM(err, status, routine, subroutine) {                       \
00198     if (status != SUCCESS) {                                              \
00199         addError(err, status, routine, subroutine, __FILE__, __LINE__);   \
00200     }                                                                     \
00201 }
00202 
00203 //Versions of the above macros which are specialized for primitives:
00204 #define newErrPrimFatalM(err, level, msg) {                               \
00205     newError(&returnCode, err, level,                                     \
00206              primParameters[primData->primIndex].name, msg,               \
00207              __FILE__, __LINE__);                                         \
00208     if (FATAL(returnCode)) { return returnCode; }                         \
00209 }
00210 
00211 #define addErrPrimFatalM(err, status, subroutine) {                       \
00212     if (status != SUCCESS) {                                              \
00213         addError(&err, status, primParameters[primData->primIndex].name,  \
00214                  subroutine, __FILE__, __LINE__);                         \
00215         if (FATAL(returnCode)) { return returnCode; }                     \
00216     }                                                                     \
00217 }
00218 
00219 #define newErrPrimM(err, level, msg) {                                    \
00220     newError(&returnCode, err, level,                                     \
00221              primParameters[primData->primIndex].name, msg,               \
00222              __FILE__, __LINE__);                                         \
00223 }
00224 
00225 #define addErrPrimM(err, status, subroutine) {                            \
00226     if (status != SUCCESS) {                                              \
00227         addError(&err, status, primParameters[primData->primIndex].name,  \
00228                  subroutine, __FILE__, __LINE__);                         \
00229     }                                                                     \
00230 }
00231 
00232 /******************************** Simulation Macros: ********************************/
00233 #if (defined(SIM))
00234     extern uint32 doSendCfg; //dpsf: see simulation.c for discussion.
00235     extern uint32 simTriggerSent, simEvtXmit, simEvtReceived;
00236     #define simulationM_cfg() {if (!doSendCfg) return SUCCESS; }
00237 
00238     /* Interrupts (async) disabled and timers are paused/resumed outside the function
00239        calls to create as little interference as is possible with the timing of the
00240        main routines. */
00241 
00242     //Check the FPGA register just accessed:
00243     #define simFpgaReadM(reg, wid, bit, val)  {   \
00244         UINT8 setGie= FALSE;                      \
00245         if (CSR & 1) {                            \
00246             CSR&= ~1;                             \
00247             setGie= TRUE;                         \
00248             pauseTimer(0);                        \
00249             pauseTimer(1);                        \
00250         }                                         \
00251         simFpgaCheck(TRUE, reg, wid, bit, val);   \
00252         if (setGie) {                             \
00253             resumeTimer(1);                       \
00254             resumeTimer(0);                       \
00255             CSR|= 1;                              \
00256         }                                         \
00257     }
00258     #define simFpgaWriteM(reg, wid, bit, val) {   \
00259         UINT8 setGie= FALSE;                      \
00260         if (CSR & 1) {                            \
00261             CSR&= ~1;                             \
00262             setGie= TRUE;                         \
00263             pauseTimer(0);                        \
00264             pauseTimer(1);                        \
00265         }                                         \
00266         simFpgaCheck(FALSE, reg, wid, bit, val);  \
00267         if (setGie) {                         \
00268             resumeTimer(1);                       \
00269             resumeTimer(0);                       \
00270             CSR|= 1;                              \
00271         }                                         \
00272     }
00273 
00274     //Calls a function which sets up the simulation for an "event".
00275     #define simTriggerArmM(sdsp) {                \
00276         UINT8 setGie= FALSE;                      \
00277         if (CSR & 1) {                            \
00278             CSR&= ~1;                             \
00279             setGie= TRUE;                         \
00280             pauseTimer(0);                        \
00281             pauseTimer(1);                        \
00282         }                                         \
00283         simTriggerArm(sdsp);                      \
00284         if (setGie) {                             \
00285             resumeTimer(1);                       \
00286             resumeTimer(0);                       \
00287             CSR|= 1;                              \
00288         }                                         \
00289     }
00290 
00291 #else
00292     //Empty macros => do not affect non-simulation code at all.
00293     #define simFpgaWriteM(reg, wid, bit, val) { }
00294     #define simFpgaReadM(reg, wid, bit, val) { }
00295     #define simulationM_cfg() { }
00296     #define simTriggerArmM(sdsp)  { }
00297 #endif
00298 
00299 
00300 /********************************** Timing Macros: **********************************/
00301 /* SendConfig timing macros; these use the configuration-timing structure defined
00302    in timing.h: */
00303 #define timingMacro_cfg0() { \
00304     t0= TIMER_getCount(timer1);  \
00305     setMem((UINT32 *) &cfgTiming, SIZEOF(CfgTiming), 0); \
00306 }
00307 
00308 //Simulator has a bug & goes bezerk in SIM code if full macros are used:
00309 #if defined(SIM)
00310 //#if (defined(SCT_ROD) && defined(SIM))
00311     #define timingMacro_cfg1() { ++cfgTiming.ngbl;}
00312     #define timingMacro_cfg2() { ; }
00313     #define timingMacro_cfg3() { ; }
00314     #define timingMacro_cfg4() { ; }
00315     #define timingMacro_cfg5() { ; }
00316     #define timingMacro_cfg6() { ; }
00317 
00318 #else
00319     #define timingMacro_cfg1() { \
00320         ++cfgTiming.ngbl; \
00321         t1= TIMER_getCount(timer1);  len1= cb->bitIndex; \
00322     }
00323     
00324     #define timingMacro_cfg2() { \
00325         cfgTiming.gbl_mk=  delta_t(t1); \
00326         cfgTiming.gbl_len= cb->bitIndex -len1; \
00327     }
00328     
00329     #ifdef PIXEL_ROD
00330         #define timingMacro_cfg3() { \
00331             ++cfgTiming.nreg; \
00332             t1= TIMER_getCount(timer1);  len1= cb->bitIndex; \
00333         }
00334         
00335         #define timingMacro_cfg4() { \
00336             cfgTiming.reg_mk=  delta_t(t1); \
00337             cfgTiming.reg_len= cb->bitIndex -len1; \
00338         }
00339     #endif
00340     
00341     #define timingMacro_cfg5() { \
00342         t1= TIMER_getCount(timer1);  len1= cb->bitIndex; \
00343     }
00344     
00345     #define timingMacro_cfg6() { \
00346         cfgTiming.enableDT_mk=  delta_t(t1); \
00347         cfgTiming.enableDT_len= cb->bitIndex -len1; \
00348     }
00349 #endif
00350 
00351 
00352 #define timingMacro_cfg7() { \
00353     cfgTiming.total= delta_t(t0); \
00354     cfgTiming.setup= cfgTiming.total -cfgTiming.xmit; \
00355     cfgTiming.cfg= cfgTiming.total -cfgTiming.setup; \
00356 }
00357 
00358 #define timingMacro_cfg8() { \
00359     if (GET_RBIT(DIAGNOSTIC_REG, DR_MODULE_CFG_LOOP)) { \
00360         sprintf(genStr, "%s\n  %s %d %d (%d %d)\n  %s %d %d\n  %s %d %d\n  %s %d %d\n  %s %d %d\n",  \
00361             "cfg timing info:",  \
00362             "total & setup times (ngbl, nreg): ",  cfgTiming.total, cfgTiming.setup, cfgTiming.ngbl, cfgTiming.nreg, \
00363             "interleaving & transmission times: ", cfgTiming.il, cfgTiming.xmit, \
00364             "EDT mk len: ",  cfgTiming.enableDT_mk, cfgTiming.enableDT_len, \
00365             "gbl mk len: ",  cfgTiming.gbl_mk, cfgTiming.gbl_len, \
00366             "reg mk len: ",  cfgTiming.reg_mk, cfgTiming.reg_len \
00367             );     \
00368         newInformation(__FILE__, __LINE__, genStr); \
00369     } \
00370 }
00371 
00372 /********************************** Waiting Macros: *********************************/
00373 #define waitingMacro_cfg0() { \
00374     if (GET_RBIT(DIAGNOSTIC_REG, DR_MODULE_CFG_LOOP)) { \
00375         sprintf(genStr, "beginning loop= %d: sp= %d, jmax= %d.\n", loop, sp, jMax); \
00376         newInformation(__FILE__, __LINE__, genStr); \
00377         waitRegister(DIAGNOSTIC_REG, DR_STEP_TRIGGER, CONTEXT_ALL); \
00378     } \
00379 }
00380 
00381 #define waitingMacro_cfg1() { \
00382     if (GET_RBIT(DIAGNOSTIC_REG, DR_MODULE_CFG_LOOP)) { \
00383         if ((sp != SP_BOTH) || (j == (jMax -1)) ) { \
00384             sprintf(genStr, "%s  %s%d, %d%s  %s0x%08x 0x%08x  %s0x%x 0x%x %s", \
00385                     "Prep to interleave/send stream. ", \
00386                     "mod[2]= ", mod[0], mod[1], ".\n", \
00387                     "stream[2]= ", (UINT32) stream[0], (UINT32) stream[1], \
00388                     "streamLen[2]= ", streamLen[0], streamLen[1], ".\n");  \
00389             newInformation(__FILE__, __LINE__, genStr); \
00390             waitRegister(DIAGNOSTIC_REG, DR_STEP_TRIGGER, CONTEXT_ALL); \
00391         } \
00392     } \
00393 }
00394 
00395 #define waitingMacro_cfg0a() { \
00396     if (GET_RBIT(DIAGNOSTIC_REG, DR_MODULE_CFG_LOOP)) { \
00397         sprintf(genStr, "sigh, cidx, nj, nMod, regSel, index= 0x%x 0x%x 0x%x 0x%x 0x%x\n", cidx, nj, nMod, regSelect, cmdBuffer[port].bitIndex); \
00398         newInformation(__FILE__, __LINE__, genStr); \
00399         waitRegister(DIAGNOSTIC_REG, DR_STEP_TRIGGER, CONTEXT_ALL); \
00400     } \
00401 }
00402 
00403 #define waitingMacro_cfg0b() { \
00404     if (GET_RBIT(DIAGNOSTIC_REG, DR_MODULE_CFG_LOOP)) { \
00405         sprintf(genStr, "sigh!, bit index= 0x%x\n", cmdBuffer[port].bitIndex); \
00406         newInformation(__FILE__, __LINE__, genStr); \
00407         waitRegister(DIAGNOSTIC_REG, DR_STEP_TRIGGER, CONTEXT_ALL); \
00408     } \
00409 }
00410 
00411 #define waitingMacro_cfg0c() { \
00412     if (GET_RBIT(DIAGNOSTIC_REG, DR_MODULE_CFG_LOOP)) { \
00413         sprintf(genStr, "edt!, bit index= 0x%x\n", cmdBuffer[port].bitIndex); \
00414         newInformation(__FILE__, __LINE__, genStr); \
00415         waitRegister(DIAGNOSTIC_REG, DR_STEP_TRIGGER, CONTEXT_ALL); \
00416     } \
00417 }
00418 
00419 #define waitingMacro_cfg2() { \
00420     if (GET_RBIT(DIAGNOSTIC_REG, DR_MODULE_CFG_LOOP)) { \
00421         sprintf(genStr, "leaving sendConfigSet...\n"); \
00422         newInformation(__FILE__, __LINE__, genStr); \
00423         waitRegister(DIAGNOSTIC_REG, DR_STEP_TRIGGER, CONTEXT_ALL); \
00424     } \
00425 }
00426 
00427 #endif /* Multiple-inclusion protection */

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