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registerIndices.h

00001 /************************************************************************************
00002  * registerIndices.h
00003  *
00004  *  synopsis: Constructs ID numbers, sequential integers starting at 0, for each
00005  *           register in the DSPs memory map.  LAST_ROD_REG, defined below, is the
00006  *           ID of the last register; it is one less than the number of registers. The
00007  *           IDs run from 0 to LAST_ROD_REG.  An array of structures, rodRegister[],
00008  *           which contains information about the registers is indexed by these IDs.
00009  *
00010  *  related files:
00011  *   accessRegister.c: Routines for reading and writing to the registers in the DSP
00012  *                     memory map and for initializing the rodRegister array with
00013  *                     information about each register, e.g. its register's address.
00014  *   rodConfiguration.h: Has constants which are specific to each ROD, e.g. is it SCT
00015  *                      or pixel, how many formatter FPGAs are there...
00016  *
00017  *  Damon Fasching, UW Madison                            fasching@wisconsin.cern.ch
00018  *  Douglas Ferguson, UW Madison   (510) 486-5230         dpferguson@lbl.gov
00019  *
00020  *  modifications/bugs    
00021  *   - Modified the router registers to reflect new map (changes to trapping
00022  *     registers, and event-based trapping).                           18.04.02 dpsf
00023  *   - changed the BOC section to reflect the revised map. Extra space has been
00024  *     inserted in the MDSP register map between and within sections to allow
00025  *     for future changes without having to completely re-write the test stand
00026  *     rwRegField text (and any existing primitives & lists on the test stand which
00027  *     use rwRegField. Thus, the first register of each section is defined as (for ex.):
00028  *     #define RTR_TRAP_CMND_0(slv)       (17 + EVT_MEM_STATUS + slv)  -- 16 spare
00029  *     indices have been inserted between the EFB registers and the router registers. 
00030  *     If extra registers are needed in any section, they should be put in the
00031  *     appropriate spare slot; the definition of the first register of the next
00032  *     section should be left AS IS. Just check to make sure that the spare space
00033  *     has not been exceeded (highly unlikely, since changes from now on should be
00034  *     minor).                                                         24.04.02 dpsf
00035  *   - Updated the formatter registers here and in accessRegister.c to
00036  *     match the new formatter VHDL code.                             02.04.03 dpsf
00037  *   - Updated the registers here and in accessRegister.c to
00038  *     reflect a few new ROD registers & bit re-definitions.          04.04.03 dpsf
00039  ************************************************************************************/
00040 #ifndef REGISTER_INDICES
00041 #define REGISTER_INDICES
00042 
00043 #include "rodConfiguration.h"
00044 
00045 #define NUM_FE_OCC_REGS      3
00046 #define NUM_DATA_LINK_MASKS  3
00047 #define NUM_DM_LUTS          0xC 
00048 #define NUM_FE_OCC_STAT_REGS 8
00049 #define N_MODE_BITS          2
00050 #define N_ROD_MASK_LUTS      8
00051 #define N_ROD_SP             2
00052 #define N_ROD_SP_REG         2
00053 /* Formatter FPGA registers */
00054 
00055 #define FMT_LINK_EN(fmt)              (fmt)
00056 #define FMT_EXP_MODE_EN(fmt)          (1 +(FMT_LINK_EN(FORMATTERS_PER_ROD-1)) +fmt)
00057 #define FMT_CONFIG_MODE_EN(fmt)       (1 +(FMT_EXP_MODE_EN(FORMATTERS_PER_ROD-1)) +fmt)
00058 #define FMT_EDGE_MODE_EN(fmt)         (1 +(FMT_CONFIG_MODE_EN(FORMATTERS_PER_ROD-1)) +fmt)
00059 #define FMT_READOUT_TIMEOUT(fmt)      (1 +(FMT_EDGE_MODE_EN(FORMATTERS_PER_ROD-1)) +fmt)
00060 #define FMT_DATA_OVERFLOW_LIMIT(fmt)  (1 +(FMT_READOUT_TIMEOUT(FORMATTERS_PER_ROD-1)) +fmt)
00061 #define FMT_HEADER_TRAILER_LIMIT(fmt) (1 +(FMT_DATA_OVERFLOW_LIMIT(FORMATTERS_PER_ROD-1)) +fmt)
00062 #define FMT_ROD_BUSY_LIMIT(fmt)       (1 +(FMT_HEADER_TRAILER_LIMIT(FORMATTERS_PER_ROD-1)) +fmt)
00063 #define FMT_PXL_LINK_L1A_CNT(fmt)     (1 +(FMT_ROD_BUSY_LIMIT(FORMATTERS_PER_ROD-1)) +fmt)
00064 #define FMT_PXL_BANDWIDTH(fmt)        (1 +(FMT_PXL_LINK_L1A_CNT(FORMATTERS_PER_ROD-1)) +fmt)
00065 #define FMT_LINK_DATA_TEST_MUX(fmt)   (33 +(FMT_PXL_BANDWIDTH(FORMATTERS_PER_ROD-1)) +fmt)
00066 /* +4*8 reserved IDs */
00067 #define FMT_MB_DIAG_REN(fmt)          (1 +(FMT_LINK_DATA_TEST_MUX(FORMATTERS_PER_ROD-1)) +fmt)
00068 #define FMT_LINK_OCC_CNT(fmt,lnk)     (1 +(FMT_MB_DIAG_REN(FORMATTERS_PER_ROD-1)) \
00069                                          +(fmt*LINKS_PER_FORMATTER) +lnk)
00070 
00071 #define FMT_TIMEOUT_ERR(fmt)          (1 +(FMT_LINK_OCC_CNT((FORMATTERS_PER_ROD-1), \
00072                                                             (LINKS_PER_FORMATTER-1))) \
00073                                         +fmt)
00074 #define FMT_DATA_OVERFLOW_ERR(fmt)    (1 +(FMT_TIMEOUT_ERR(FORMATTERS_PER_ROD-1)) +fmt)
00075 #define FMT_HEADER_TRAILER_ERR(fmt)   (1 +(FMT_DATA_OVERFLOW_ERR(FORMATTERS_PER_ROD-1)) +fmt)
00076 #define FMT_ROD_BUSY_ERR(fmt)         (1 +(FMT_HEADER_TRAILER_ERR(FORMATTERS_PER_ROD-1)) +fmt)
00077 
00078 #define FMT_DATA_FMT_STATUS(fmt)      (1 +(FMT_ROD_BUSY_ERR(FORMATTERS_PER_ROD-1)) +fmt)
00079 #define FMT_STATUS(fmt)               (1 +(FMT_DATA_FMT_STATUS(FORMATTERS_PER_ROD-1)) +fmt)
00080 #define FMT_VERSION(fmt)              (1 +(FMT_STATUS(FORMATTERS_PER_ROD-1)) +fmt)
00081 #define FMT_MODEBIT_STAT_05(fmt)      (1 +(FMT_VERSION(FORMATTERS_PER_ROD-1)) +fmt)
00082 #define FMT_MODEBIT_STAT_6B(fmt)      (1 +(FMT_MODEBIT_STAT_05(FORMATTERS_PER_ROD-1)) +fmt)
00083 
00084 
00085 /* Event Fragment Builder FPGA registers */
00086 #define EFB_ERROR_MASK(efb, lnk) (25 + FMT_MODEBIT_STAT_6B(FORMATTERS_PER_ROD-1) + \
00087                                   efb*DATA_LINKS_PER_EFB + lnk)
00088 #define FORMAT_VRSN          (1 + EFB_ERROR_MASK((EFBS_PER_ROD-1),(DATA_LINKS_PER_EFB-1)))
00089 #define SOURCE_ID            (1 + FORMAT_VRSN) // was FORMAT_VRSN_MSB
00090 #define RUN_NUMBER           (1 + SOURCE_ID)   // was SOURCE_ID_LSB
00091 #define EFB_UNUSED           (1 + RUN_NUMBER)  // was SOURCE_ID_MSB
00092 #define EFB_CMND_0           (1 + EFB_UNUSED)
00093 #define EFB_FORMATTER_STAT   (1 + EFB_CMND_0)
00094 #define EFB_RUNTIME_STAT_REG (1 + EFB_FORMATTER_STAT)
00095 #define EVENT_HEADER_DATA    (1 + EFB_RUNTIME_STAT_REG)
00096 #define EV_FIFO_DATA1        (1 + EVENT_HEADER_DATA)
00097 #define EV_FIFO_DATA2        (1 + EV_FIFO_DATA1)
00098 
00099 #define EVT_MEM_MODE         (1 + EV_FIFO_DATA2)
00100 #define EVT_MEM_CMND_STAT    (1 + EVT_MEM_MODE)
00101 #define EVT_MEM_RESET        (1 + EVT_MEM_CMND_STAT)
00102 #define EVT_MEM_FLAGS        (1 + EVT_MEM_RESET)
00103 #define EVT_MEM_A_WRD_CNT    (1 + EVT_MEM_FLAGS)
00104 #define EVT_MEM_B_WRD_CNT    (1 + EVT_MEM_A_WRD_CNT)
00105 #define EVT_MEM_PLAY_EVENT   (1 + EVT_MEM_B_WRD_CNT)
00106 #define EVT_MEM_STATUS       (1 + EVT_MEM_PLAY_EVENT)
00107 #define EFB_EVT_CNT          (1 + EVT_MEM_STATUS)
00108 #define EFB_BANDWIDTH_CNT    (1 + EFB_EVT_CNT)
00109 #define EFB_CODE_VERSION     (1 + EFB_BANDWIDTH_CNT)
00110 
00111 /* Router FPGA registers- note that addresses in router are done in 4 blocks
00112  * (1 block per slv) of CMD0(slv), CMD1(slv), .... INT_DELAY _CNT, ..., while here
00113  * they are indexed (used in the rodRegister structure in accessRegister.c) as
00114  * CMD0(0), ... CMD0(3), CMD1(0)...  The addressing for rodRegister is done in
00115  * accessRegister.c  dpsf. */
00116 #define RTR_TRAP_CMND_0(slv)       (14 + EFB_CODE_VERSION + slv)
00117 #define RTR_TRAP_CMND_1(slv)       (1 + RTR_TRAP_CMND_0(N_SDSP-1)  + slv)
00118 #define RTR_TRAP_RESET(slv)        (1 + RTR_TRAP_CMND_1(N_SDSP-1)  + slv) 
00119 #define RTR_TRAP_STATUS(slv)       (1 + RTR_TRAP_RESET(N_SDSP-1)   + slv)
00120 #define RTR_TRAP_MATCH_0(slv)      (1 + RTR_TRAP_STATUS(N_SDSP-1)  + slv)
00121 #define RTR_TRAP_MOD_0(slv)        (1 + RTR_TRAP_MATCH_0(N_SDSP-1) + slv)
00122 #define RTR_TRAP_MATCH_1(slv)      (1 + RTR_TRAP_MOD_0(N_SDSP-1)   + slv)
00123 #define RTR_TRAP_MOD_1(slv)        (1 + RTR_TRAP_MATCH_1(N_SDSP-1) + slv)
00124 #define RTR_TRAP_XFR_FRM_SIZE(slv) (1 + RTR_TRAP_MOD_1(N_SDSP-1)   + slv)
00125 #define RTR_TRAP_FIFO_WRD_CNT(slv) (1 + RTR_TRAP_XFR_FRM_SIZE(N_SDSP-1) + slv)
00126                    /* 1 unused half-word/slv in router, reserved here (1 word/hw) */
00127 #define RTR_TRAP_EVT_CNT(slv)      (5 + RTR_TRAP_FIFO_WRD_CNT(N_SDSP-1) + slv)
00128 #define RTR_TRAP_INT_DELAY_CNT(slv) (1 + RTR_TRAP_EVT_CNT(N_SDSP-1) + slv)
00129                       /* 3 unused hw before beginning of next slave address block */
00130 #define RTR_CMND_STAT              (13 + RTR_TRAP_INT_DELAY_CNT(N_SDSP-1))
00131 #define RTR_SLNK_ATLAS_DUMP_MATCH  (1 + RTR_CMND_STAT)
00132 #define RTR_SLNK_ROD_DUMP_MATCH    (1 + RTR_SLNK_ATLAS_DUMP_MATCH)
00133 
00134 #define RTR_CODE_VERSION           (1 + RTR_SLNK_ROD_DUMP_MATCH)
00135 #define RTR_OUTPUT_SIGNAL_MUX      (1 + RTR_CODE_VERSION)
00136 
00137 /* ROD resources interface FPGA (RRIF) registers */
00138 #define RRIF_CODE_VERSION         (16 + RTR_OUTPUT_SIGNAL_MUX)
00139 #define RRIF_CMND_1               (1 + RRIF_CODE_VERSION)
00140 #define RRIF_CMND_0               (1 + RRIF_CMND_1)
00141 #define ROD_MODE_REG              (1 + RRIF_CMND_0)
00142 #define FE_MASK_LUT_SELECT        (1 + ROD_MODE_REG)
00143 #define RRIF_STATUS_1             (1 + FE_MASK_LUT_SELECT)
00144 #define RRIF_STATUS_0             (1 + RRIF_STATUS_1)
00145 #define FE_CMND_MASK_0_LO         (3 + RRIF_STATUS_0)
00146 #define FE_CMND_MASK_0_HI         (1 + FE_CMND_MASK_0_LO)
00147 #define FE_CMND_MASK_1_LO         (1 + FE_CMND_MASK_0_HI)
00148 #define FE_CMND_MASK_1_HI         (1 + FE_CMND_MASK_1_LO)
00149 #define CALSTROBE_DELAY           (1 + FE_CMND_MASK_1_HI)
00150 #define CAL_CMND                  (1 + CALSTROBE_DELAY) 
00151 #define FRMT_RMB_STATUS           (3 + CAL_CMND)
00152 #define EFB_DM_FIFO_FLAG_STA      (2 + FRMT_RMB_STATUS)
00153 #define EFB_DM_WC_STA_REG         (1 + EFB_DM_FIFO_FLAG_STA)
00154 #define INP_MEM_CTRL              (1 + EFB_DM_WC_STA_REG)
00155 #define DBG_MEM_CTRL              (1 + INP_MEM_CTRL)
00156 #define CFG_READBACK_CNT          (1 + DBG_MEM_CTRL)
00157 #define IDE_MEM_CTRL              (2 + CFG_READBACK_CNT)
00158 #define IDE_MEM_STAT              (1 + IDE_MEM_CTRL)
00159 #define INTRPT_TO_SLV             (7 + IDE_MEM_STAT)
00160 #define INTRPT_FROM_SLV           (1 + INTRPT_TO_SLV)
00161 
00162 #define DFLT_ROD_EVT_TYPE         (1 + INTRPT_FROM_SLV)
00163 #define CRTV_ROD_EVT_TYPE         (1 + DFLT_ROD_EVT_TYPE)
00164 #define CAL_L1_TRIG_TYPE_0        (1 + CRTV_ROD_EVT_TYPE)
00165 #define CAL_L1_TRIG_TYPE_1        (1 + CAL_L1_TRIG_TYPE_0)
00166 #define CAL_L1_ID_0               (1 + CAL_L1_TRIG_TYPE_1)
00167 #define CAL_L1_ID_1               (1 + CAL_L1_ID_0)
00168 #define CAL_BCID                  (1 + CAL_L1_ID_1)
00169 
00170 #define FE_OCC_CNTR_RESET(msk)    (16 + CAL_BCID + msk) 
00171 #define FE_OCC_CNTR_LOAD(msk)     (1 + FE_OCC_CNTR_RESET(NUM_FE_OCC_REGS-1) + msk)
00172 #define FE_OCC_LOAD_VALUE         (1 + FE_OCC_CNTR_LOAD(NUM_FE_OCC_REGS-1))
00173 #define DATA_LINK_MASK(msk)       (1 + msk + FE_OCC_LOAD_VALUE)
00174 #define FE_OCC_CNTR(occ)          (1 + DATA_LINK_MASK(NUM_FE_OCC_REGS-1) + occ)
00175 
00176 #define DM_DFLT_LUT(mbLut)        (16 + FE_OCC_CNTR(NUM_FE_OCC_STAT_REGS-1) + mbLut)
00177 #define DM_CRTV_LUT(mbLut)        (1 + DM_DFLT_LUT(NUM_DM_LUTS-1) + mbLut)
00178 #define CORRECTED_EVENTS_FIFO     (1 + DM_CRTV_LUT(NUM_DM_LUTS-1))
00179 
00180 
00181 #define RMB_DFLT_LUT(lutset, fmt, mb)  (16 + CORRECTED_EVENTS_FIFO + \
00182          (FORMATTERS_PER_ROD*N_MODE_BITS)*lutset  +(N_MODE_BITS)*fmt +mb)
00183 
00184 #define RMB_CRTV_LUT(lutset, fmt, mb)  (1 + \
00185          RMB_DFLT_LUT((N_ROD_MASK_LUTS-1),(FORMATTERS_PER_ROD-1),(N_MODE_BITS-1)) + \
00186          (FORMATTERS_PER_ROD*N_MODE_BITS)*lutset  +(N_MODE_BITS)*fmt +mb)
00187 
00188 /* Old definitions for backward compatability; default set is #0 */
00189 #define RMB0_DFLT_LUT(fmt)    RMB_DFLT_LUT(0, fmt, 0)
00190 #define RMB1_DFLT_LUT(fmt)    RMB_DFLT_LUT(0, fmt, 1)
00191 #define RMB0_CRTV_LUT(fmt)    RMB_CRTV_LUT(0, fmt, 0)
00192 #define RMB1_CRTV_LUT(fmt)    RMB_CRTV_LUT(0, fmt, 1)
00193 
00194 #define CMND_MASK_LUT(lutset, sp, lohi) (1 + \
00195          RMB_CRTV_LUT((N_ROD_MASK_LUTS-1),(FORMATTERS_PER_ROD-1),(N_MODE_BITS-1)) + \
00196          (N_ROD_SP*N_ROD_SP_REG)*lutset  +(N_ROD_SP_REG)*sp +lohi)
00197 
00198 
00199 
00200 
00201 
00202 
00203 
00204 /* BOC (optocard) registers */
00205 #define FIRST_BOC_REG             (16 + CMND_MASK_LUT((N_ROD_MASK_LUTS-1),(N_ROD_SP-1),(N_ROD_SP_REG-1)))
00206 
00207 #define STREAM_INHIBIT_MASK(clnk) (FIRST_BOC_REG + clnk)
00208 #define MARK_SPACE(clnk)          (1 + STREAM_INHIBIT_MASK(CTRL_LINKS_PER_ROD-1) + clnk)
00209 #define COARSE_DELAY(clnk)        (1 + MARK_SPACE(CTRL_LINKS_PER_ROD - 1) + clnk)
00210 #define FINE_DELAY(clnk)          (1 + COARSE_DELAY(CTRL_LINKS_PER_ROD - 1) + clnk)
00211 
00212 #define LASER_CURR_DAC(clnk)      (1 + FINE_DELAY(CTRL_LINKS_PER_ROD - 1) + clnk)
00213 #define IN_LINK_DATA_DELAY(lnk)   (1 + LASER_CURR_DAC(CTRL_LINKS_PER_ROD - 1) + lnk)
00214 
00215 #define BPM_CLOCK_PHASE           (1 + IN_LINK_DATA_DELAY(DATA_LINKS_PER_ROD-1))
00216 #define BREG_CLOCK_PHASE          (3 + BPM_CLOCK_PHASE)
00217 #define VERNIER_CLOCK_STEP_PHASE0 (1 + BREG_CLOCK_PHASE)
00218 #define VERNIER_CLOCK_STEP_PHASE1 (1 + VERNIER_CLOCK_STEP_PHASE0)
00219 
00220 #define STROBE_DELAY(sdlnk)       (3 + VERNIER_CLOCK_STEP_PHASE1 + (sdlnk ))
00221 #define IN_DATA_RX_THRESH_DAC(lnk)  (1 + STROBE_DELAY(STROBE_DELAYS_PER_BOC-1) + lnk)
00222 
00223 #define BOC_RESET                 (1 + IN_DATA_RX_THRESH_DAC(DATA_LINKS_PER_ROD-1))
00224 #define BOC_STATUS                (1 + BOC_RESET)
00225 #define BPM_RESET                 (3 + BOC_STATUS)
00226 #define TX_DAC_CLEAR              (4 + BPM_RESET)
00227 #define RX_DAC_CLEAR              (1 + TX_DAC_CLEAR)
00228 #define RX_DATA_MODE              (2 + RX_DAC_CLEAR)
00229 #define VERNIER_CLOCK_FINE_PHASE  (5 + RX_DATA_MODE)
00230 #define CLOCK_CONTROL_BITS        (2 + VERNIER_CLOCK_FINE_PHASE)
00231 
00232 #define BOC_FIRMWARE_VERSION      (3 + CLOCK_CONTROL_BITS)
00233 #define BOC_HARDWARE_VERSION      (1 + BOC_FIRMWARE_VERSION)
00234 #define BOC_MODULE_TYPE           (1 + BOC_HARDWARE_VERSION)
00235 #define BOC_MANUFACTURER          (1 + BOC_MODULE_TYPE)
00236 #define BOC_SERIAL_NUMBER         (13 + BOC_MANUFACTURER)
00237 
00238 #define LAST_BOC_REG              (BOC_SERIAL_NUMBER)
00239 #define LAST_ROD_REG              (LAST_BOC_REG)
00240 
00241 /* Define the fields (widths and locations) in each register and their legal values. */
00242 
00243 /* FMT_READOUT_TIMEOUT */
00244 #define FMT_READOUT_TIMEOUT_O          0
00245 #define FMT_READOUT_TIMEOUT_W          8
00246 
00247 /* FMT_DATA_OVERFLOW_LIMIT */
00248 #define FMT_DATA_OVERFLOW_LIMIT_O      0
00249 #define FMT_DATA_OVERFLOW_LIMIT_W      9
00250 
00251 /* FMT_HEADER_TRAILER_LIMIT */
00252 #define FMT_HEADER_TRAILER_LIMIT_O     0
00253 #define FMT_HEADER_TRAILER_LIMIT_W     5
00254 
00255 /* FMT_ROD_BUSY_LIMIT */
00256 #define FMT_ROD_BUSY_LIMIT_O           0
00257 #define FMT_ROD_BUSY_LIMIT_W           8
00258 
00259 /* FMT_PXL_LINK_L1A_CNT */
00260 #define FMT_PXL_LINK_W                 4
00261 #define FMT_PXL_LINK0_O                0
00262 #define FMT_PXL_LINK1_O                4
00263 #define FMT_PXL_LINK2_O                8
00264 #define FMT_PXL_LINK3_O                12
00265 
00266 /* FMT_PXL_BANDWIDTH */
00267 #define FMT_PXL_BANDWIDTH_W            2
00268 #define FMT_PXL_BANDWIDTH_40MHZ        0
00269 #define FMT_PXL_BANDWIDTH_80MHZ        1
00270 #define FMT_PXL_BANDWIDTH_160MHZ       2
00271 
00272 /* FMT_LINK_DATA_TEST_MUX */
00273 #define FMT_LINK_DATA_TEST_MUX_O       0
00274 #define FMT_LINK_DATA_TEST_MUX_W       4
00275 
00276 /* FMT_LINK_OCC_CNT */
00277 #define FMT_LINK_OCC_CNT_O             0
00278 #define FMT_LINK_OCC_CNT_W             9
00279 
00280 /* FMT_STATUS */
00281 #define FMT_STAT_TRIG_CNT_O            0
00282 #define FMT_STAT_TRIG_CNT_W            5
00283 /* bit 5 not used */
00284 #define FMT_STAT_LINK_MB_FIFO_NE_O     6
00285 #define FMT_STAT_LINK_MB_FIFO_FULL_O   7
00286 #define FMT_STAT_ACTIVE_LINK_O         8
00287 #define FMT_STAT_ACTIVE_LINK_W         4
00288 #define FMT_STAT_CHIP_HAS_TOKEN_O     12
00289 #define FMT_STAT_HOLD_OUTPUT_O        13
00290 
00291 #define FMT_STAT_MASTER_SLAVE_O       14
00292 #define FMT_STAT_DLL_LOCKED_O         15
00293 
00294 /* FMT_VERSION */
00295 #define FMT_CODE_VERSION_O            0
00296 #define FMT_CODE_VERSION_W            8
00297 #define FMT_BOARD_VERSION_O           8
00298 #define FMT_BOARD_VERSION_W           8
00299 
00300 
00301 /* EFB_ERROR_MASK: */
00302 #define EFB_HEADER_BIT_ERR_O               0
00303 #define EFB_TRAILER_BIT_ERR_O              1
00304 #define EFB_FLAGGED_ERR_O                  2
00305 #define EFB_SYNC_ERR_O                     3
00306 #if defined(SCT_ROD)
00307     #define EFB_CONDENSED_MODE_PATTERN_ERR_O   4
00308 #elif defined(PIXEL_ROD)
00309     #define EFB_MCC_ERR_O                      4
00310 #endif
00311 #define EFB_L1ID_ERR_O                     5
00312 #define EFB_BCID_ERR_O                     6
00313 #define EFB_TIMEOUT_ERR_O                  7
00314 #define EFB_ALMOST_FULL_ERR_O              8
00315 #define EFB_DATA_OVERFLOW_ERR_O            9
00316 #define EFB_NONSEQUENTIAL_CHIP_ERR_O       10
00317 #if defined(SCT_ROD)
00318     #define EFB_INVALID_CHIP_ERR_O             11
00319 #elif defined(PIXEL_ROD)
00320     #define EFB_INVALID_ROW_ERR_O              11
00321 #endif
00322 #if defined(SCT_ROD)
00323 #elif defined(PIXEL_ROD)
00324     #define EFB_INVALID_COLUMN_ERR_O           12
00325     #define EFB_MCC_EMPTY_EVT_ERR_O            13
00326 #endif
00327 
00328 #define EFB_DYNAMIC_MASK_STATUS_O          14
00329 #define EFB_DYNAMIC_MASK_STATUS_W          2
00330 
00331 /* EFB_CMND_0 */
00332 #define EFB_SEND_EVENTS_O      0
00333 #define EFB_MASK_BCID_O        1
00334 #define EFB_GROUP_COUNTER_EN_O 2
00335 #define EFB_MASK_L1ID_0        3
00336 #define EFB_DATA_LINK_SEL_O    4
00337 #define EFB_DATA_LINK_SEL_W    4
00338 #define EFB_BCID_OFFSET_O      8
00339 #define EFB_BCID_OFFSET_W      8
00340 
00341 /* EFB_FORMATTER_STAT  */ 
00342 #define EFB_FORMATTER_STAT_O 0
00343 #define EFB_FORMATTER_STAT_W 8    /* one bit for each formatter FPGA */
00344 
00345 /*EFB_RUNTIME_STAT_REG*/
00346 #define  FIFO_1_ALMOST_FULL_O          0x0
00347 #define  ERR_SUM_FIFO_1_ALMOST_FULL_O  0x1
00348 #define  EV_ID_FIFO_EMP_ERR1_O         0x2
00349 #define  FIFO1_PAUSE_TO_FORMATTER_O    0x3
00350 #define  FIFO_2_ALMOST_FULL_O          0x4
00351 #define  ERR_SUM_FIFO_2_ALMOST_FULL_O  0x5
00352 #define  EV_ID_FIFO_EMP_ERR2_O         0x6
00353 #define  FIFO2_PAUSE_TO_FORMATTER_O    0x7
00354 #define  HALT_OUTPUT_FROM_ROUTER_O     0x8
00355 
00356 /*  EVENT_HEADER_DATA  */
00357 #define  EVENT_HEADER_DATA_O   0
00358 #define  EVENT_HEADER_DATA_W   16
00359 
00360 /* EV_FIFO_DATA1 */ 
00361 #define EV_FIFO_DATA1_O    0
00362 #define EV_FIFO_DATA1_W    12
00363 
00364 /* EV_FIFO_DATA2 */ 
00365 #define EV_FIFO_DATA2_O    0
00366 #define EV_FIFO_DATA2_W    12
00367 
00368 /* EVT_MEM_MODE (values) */
00369 #define EVT_MEM_MODE_O    0
00370 #define EVT_MEM_MODE_W    3
00371 #define DATA_TAKING     0x0     /* normal data path */
00372 #define PLAY_TO_ROUTER  0x1     /* load via rod bus, play EVENT_MEM event to router */
00373 #define RODBUS_ACCESS   0x2     /* load via rod bus, read via rod bus */
00374 #define TRAP_REAL_DATA  0x4     /* play through normal data path, trap in EVENT_MEM */
00375 
00376 /* EVT_MEM_CMND_STAT */
00377 #define EVT_MEM_SEL_O       0
00378 #define EVT_MEM_SEL_W       3
00379 #define A_SELECT          0x1
00380 #define B_SELECT          0x2
00381 #define C_SELECT          0x4
00382 #define OUTPUT_FRAGMENT_O   3
00383 #define OUTPUT_FRAGMENT_W   1
00384 #define OUTPUT_FRAGMENT   0x1
00385 #define BUS_ENABLED_O       4
00386 #define BUS_ENABLED_W       3
00387 #define A_BUS_ENABLED     0x1
00388 #define B_BUS_ENABLED     0x2
00389 #define C_BUS_ENABLED     0x4
00390 
00391 /* EVT_MEM_RESET */
00392 #define RESET_EVT_MEM_O   0
00393  
00394 /* EVT_MEM_FLAGS */
00395 #define EFB_EVT_MEM_A_EMPTY_O      0
00396 #define EFB_EVT_MEM_A_AE_O         1
00397 #define EFB_EVT_MEM_A_FULL_O       2
00398 #define EFB_EVT_MEM_A_AF_O         3
00399 #define EFB_EVT_MEM_B_EMPTY_O      4
00400 #define EFB_EVT_MEM_B_AE_O         5
00401 #define EFB_EVT_MEM_B_FULL_O       6
00402 #define EFB_EVT_MEM_B_AF_O         7
00403 #define EFB_EVT_MEM_C_EMPTY_O      8
00404 #define EFB_EVT_MEM_C_FULL_O       9
00405 
00406 /* EFB_EVT_CNT */
00407 #define EFB_EVT_CNT_ID(x)   (4*x)
00408 #define EFB_EVT_CNT_ID_W     4
00409 
00410 /* EFB_BANDWIDTH_CNT */
00411 #define EFB_BANDWIDTH_CNT_DATA_0  0
00412 #define EFB_BANDWIDTH_CNT_TIME_0  16
00413 #define EFB_BANDWIDTH_CNT_W       16
00414 
00415 /* EVT_MEM_PLAY_EVENT */
00416 #define PLAY_EVENT_O  0
00417 
00418 
00419 
00420 
00421 
00422 /* RTR_TRAP_CMND_0/1(slv) (only bit 0-4 in 1) */
00423 #define RTR_TRAP_ATLAS_EVT_TYPE_O   0
00424 #define RTR_TRAP_TIM_EVT_TYPE_O     1
00425 #define RTR_TRAP_ROD_EVT_TYPE_O     2
00426 #define RTR_TRAP_ERROR_FMT_O        3
00427 #define RTR_TRAP_EXCLUSION_FLAG_O   4
00428 #define RTR_TRAP_ALL_EVT_SLINK_O    5
00429 #define RTR_TRAP_DATA_MODE_O        6
00430 
00431 /* RTR_TRAP_RESET(slv) */
00432 #define RTR_TRAP_RESET_O      0
00433 #define RTR_TRAP0_LOAD_NEW_O  1
00434 #define RTR_TRAP1_LOAD_NEW_O  2
00435 
00436 /* RTR_TRAP_STATUS(slv) */
00437 #define RTR_TRAP_ENABLE_FROM_DSP_O   0  /* READ ONLY */
00438 #define RTR_INTERRUPT_OK_FROM_DSP_O  1  /* READ ONLY */
00439 #define RTR_TRAP_FIFO_EMPTY_O        2  /* READ ONLY */
00440 #define RTR_TRAP_FIFO_FULL_O         3  /* READ ONLY */
00441 #define RTR_TRAP0_IDLE_O             4  /* READ ONLY */
00442 #define RTR_TRAP1_IDLE_O             5  /* READ ONLY */
00443 #define RTR_TRAP0_READY_O            6  /* READ ONLY */
00444 #define RTR_TRAP1_READY_O            7  /* READ ONLY */
00445 #define RTR_SLAVE_CLK_SYNC_O         8  /* READ ONLY */
00446 
00447 /* RTR_TRAP_MATCH_X(slv) (X= 0 or 1) */
00448 #define RTR_TRAP_MATCH_O      0 
00449 #define RTR_TRAP_MATCH_W      8
00450 
00451 /* RTR_TRAP_MOD_X(slv) */
00452 #define RTR_TRAP_MODULUS_O    0 
00453 #define RTR_TRAP_MODULUS_W    8
00454 #define RTR_TRAP_REMAINDER_O  8 
00455 #define RTR_TRAP_REMAINDER_W  8
00456 
00457 /* RTR_TRAP_XFR_FRM_SIZE(slv) */ 
00458 #define RTR_TRAP_XFR_FRM_SIZE_O  0
00459 #define RTR_TRAP_XFR_FRM_SIZE_W  10
00460 
00461 /* RTR_TRAP_FIFO_WRD_CNT(slv) */  
00462 #define RTR_TRAP_FIFO_WRD_CNT_O  0
00463 #define RTR_TRAP_FIFO_WRD_CNT_W  10
00464 
00465 /* RTR_TRAP_EVT_CNT(slv)   */ 
00466 #define  RTR_TRAP_EVT_CNT_O      0
00467 #define  RTR_TRAP_EVT_CNT_W      16
00468 
00469 /* RTR_TRAP_INT_DELAY_CNT(slv) */ 
00470 #define  RTR_TRAP_INT_DELAY_CNT_O       0
00471 #define  RTR_TRAP_INT_DELAY_CNT_W       6   /* delay= 25 ns per count */
00472 
00473 /* RTR_CMND_STAT */
00474 #define RTR_DUMP_ATLAS_EVT_TYPE_O       0
00475 #define RTR_DUMP_TIM_EVT_TYPE_O         1
00476 #define RTR_DUMP_ROD_EVT_TYPE_O         2
00477 #define RTR_INHIBIT_SLNK_WE_O           3
00478 #define RTR_RESET_SLNK_O                4
00479 #define RTR_SET_SLNK_TEST_O             5
00480 #define RTR_CALIB_BACK_PRES_EFB_O       6
00481 #define RTR_SLINK_DOWN_OVERRIDE_O       7
00482 /* bit 7 not used */
00483 #define RTR_SLNK_XOFF_STAT_O            8
00484 #define RTR_SLKN_BAD_STAT_O             9
00485 #define RTR_STOP_OUTPUT_O              10
00486 #define RTR_CLK_DLL_LOCKED_O           11
00487  
00488 /* RTR_SLNK_ATLAS_DUMP_MATCH */
00489 #define RTR_ATLAS_EVT_TYPE_O  0
00490 #define RTR_ATLAS_EVT_TYPE_W  8     /* ATLAS SPECIFIC EVENT TYPE FOR MATCH */
00491 #define RTR_TIM_EVT_TYPE_O    8
00492 #define RTR_TIM_EVT_TYPE_W    2     /* TIM SPECIFIC EVENT TYPE FOR MATCH*/
00493  
00494 /* RTR_SLNK_ROD_DUMP_MATCH  */  
00495 #define  RTR_SLNK_ROD_DUMP_MATCH_O   0
00496 #define  RTR_SLNK_ROD_DUMP_MATCH_W  16
00497  
00498 
00499 /* BOC Registers  */
00500 /*BOC  STREAM_INHIBIT_MASK(clnk) */  
00501 #define  BOC_STREAM_INHIBIT_O  0
00502 #define  BOC_STREAM_INHIBIT_W  1
00503 /*BOC  MARK_SPACE_(clnk) */ 
00504 #define  MARK_SPACE_O  0
00505 #define  MARK_SPACE_W  6
00506 /*BOC  COARSE_DELAY(clnk) */ 
00507 #define  COARSE_DELAY_O         0
00508 #define  COARSE_DELAY_W         5
00509 /*BOC  FINE_DELAY(clnk) */ 
00510 #define  FINE_DELAY_O           0
00511 #define  FINE_DELAY_W           7
00512 
00513 /* LASER_CURR_DAC(clnk)  */
00514 #define  LASER_CURR_DAC_O 0
00515 #define  LASER_CURR_DAC_W 8
00516 /* IN_LINK_DATA_DELAY(lnk)*/
00517 #define  IN_LINK_DATA_DELAY_O  0
00518 #define  IN_LINK_DATA_DELAY_W  8
00519 
00520 /* BPM_CLOCK_PHASE */
00521 #define  BPM_CLOCK_PHASE_O     0
00522 #define  BPM_CLOCK_PHASE_W     8
00523 /* BREG_CLOCK_PHASE */
00524 #define  BREG_CLOCK_PHASE_O     0
00525 #define  BREG_CLOCK_PHASE_W     8
00526 /* VERNIER_CLOCK_STEP_PHASE0 */
00527 #define  VERNIER_CLOCK_STEP_PHASE0_O     0
00528 #define  VERNIER_CLOCK_STEP_PHASE0_W     8
00529 /* VERNIER_CLOCK_STEP_PHASE1 */
00530 #define  VERNIER_CLOCK_STEP_PHASE1_O     0
00531 #define  VERNIER_CLOCK_STEP_PHASE1_W     8
00532 
00533 /*   STROBE_DELAY(sdlnk) */           
00534 #define   STROBE_DELAY_O        0
00535 #define   STROBE_DELAY_W        8
00536 /* IN_DATA_RX_THRESH_DAC(lnk)  */ 
00537 #define   IN_DATA_RX_THRESH_O    0
00538 #define   IN_DATA_RX_THRESH_W    8
00539 
00540 /* BOC_RESET  */
00541 #define    BOC_RESET_O       0             
00542 #define    BOC_RESET_W       1
00543 /* BOC_STATUS */
00544 #define    BOC_STATUS_O      0              
00545 #define    BOC_STATUS_W      8     /* READ ONLY */
00546 /* BPM_RESET  */
00547 #define    BPM_RESET_O       0             
00548 #define    BPM_RESET_W       1
00549 /* TX_DAC_CLEAR */
00550 #define    TX_DAC_CLEAR_O    0                
00551 #define    TX_DAC_CLEAR_W    1
00552 /* RX_DAC_CLEAR */
00553 #define    RX_DAC_CLEAR_O    0                
00554 #define    RX_DAC_CLEAR_W    1
00555 /* RX_DATA_MODE */
00556 #define    RX_DATA_MODE_O    0                
00557 #define    RX_DATA_MODE_W    3
00558 /* VERNIER_CLOCK_FINE_PHASE */
00559 #define    VERNIER_CLOCK_FINE_PHASE_O   0                 
00560 #define    VERNIER_CLOCK_FINE_PHASE_W   8
00561 /* CLOCK_CONTROL_BITS */
00562 #define    CLOCK_CONTROL_BITS_O   0                 
00563 #define    CLOCK_CONTROL_BITS_W   4
00564 
00565 /* BOC_FIRMWARE_VERSION  */
00566 #define    BOC_FIRMWARE_VERSION_O   0                  
00567 #define    BOC_FIRMWARE_VERSION_W   8    /* READ ONLY */
00568 /* BOC_HARDWARE_VERSION  */
00569 #define    BOC_HARDWARE_VERSION_O   0                  
00570 #define    BOC_HARDWARE_VERSION_W   8    /* READ ONLY */
00571 /* BOC_MODULE_TYPE  */
00572 #define    BOC_MODULE_TYPE_O   0                  
00573 #define    BOC_MODULE_TYPE_W   8         /* READ ONLY */
00574 /* BOC_MANUFACTURER  */
00575 #define    BOC_MANUFACTURER_O   0                  
00576 #define    BOC_MANUFACTURER_W   8        /* READ ONLY */
00577 /* BOC_SERIAL_NUMBER  */         
00578 #define    BOC_SERIAL_NUMBER_O  0                 
00579 #define    BOC_SERIAL_NUMBER_W  8        /* READ ONLY */
00580 
00581 
00582 
00583 /* RRIF_CMND_0 */
00584 #define FMT_MB_RST_OUT_O                 0 /*  formatter mode bits reset */
00585 #define FMT_MB_RST_OUT_W                 2 
00586 #define EFB_EDM_RST_OUT_O                2 /*  efb dynamic mask bits reset */
00587 #define INP_MEM_RST_O                    3
00588 #define DBG_MEM_A_RST_O                  4
00589 #define DBG_MEM_B_RST_O                  5 
00590 #define TIM_FIFO_RST_O                   6
00591 #define TRIG_FIFO_RST_O                  7 
00592 #define TRIG_FIFO_RETRANSMIT_O           8
00593 #define INMEM_FIFO_RETRANSMIT_O          9
00594 #define DBGMEMA_FIFO_RETRANSMIT_O        10
00595 #define DBGMEMB_FIFO_RETRANSMIT_O        11
00596 #define ECR_ID_COUNTER_RESET_O           12
00597 #define SP1_FRAME_SYNC_OFFSET_O          13
00598 #define SP1_FRAME_SYNC_OFFSET_W          5
00599 #define FSX_CLKX_OUTPUT_ENABLE_O         18
00600 //bits 19-23 not used
00601 #define SLOW_SDSP_CLOCK_ENABLE           24
00602 
00603 #define MDSP_TOUT_ENABLE                 25
00604 #define MDSP_INT4_ENABLE                 26
00605 #define MDSP_INT5_ENABLE                 27
00606 #define MDSP_INT6_ENABLE                 28
00607 #define MDSP_INT7_ENABLE                 29
00608 #define SDSP_INT_ENABLE                  30
00609 #define VME_INT_ENABLE                   31
00610 
00611 /* RRIF_CMND_1 */  
00612 #define FE_CMND_OUTPUT_ENABLE_O          0
00613 #define FE_SP0_FR_DSP_TIM_O              1 
00614 #define FE_SP0_FR_DSP                    1
00615 #define FE_SP0_FR_TIM                    0
00616 #define NEW_MASK_READY_O                 2  /* self clearing */
00617 #define FE_OCC_CNTR_O                    3  /* FE occupancy counter */
00618 #define CMD_PULSE_CTR_RESET_O            4  
00619 #define CMD_PULSE_CTR_ENABLE_O           5
00620 #define CMD_PULSE_CTR_LOAD_O             6
00621 #define TRG_DECODER_RESET_O              7
00622 #define TRG_DECODER_ENABLE_O             8
00623 #define FORM_RMB_FLUSH_O                 9
00624 #define FORM_RMB_ENABLE_XFR_O           10
00625 #define EFB_DYN_MSK_FLUSH_O             11
00626 #define EFB_DYN_MSK_ENABLE_XFR_O        12
00627 #define EFB_DYN_MSK_EVT_HDR_CNT_LD_O    13
00628 #define EFB_DYN_MSK_EVT_MSK_CNT_LD_O    14  
00629 #define TEST_BENCH_RESET_O              15
00630 #define TEST_BENCH_ENABLE_O             16
00631 #define TEST_BENCH_RUN_O                17
00632 #define SP_TRIGGER_SIGNAL_DECODER_EN_O  18  /* 0=> Off, 1=> Enabled */
00633 #define CONFIGURATION_READBACK_O        19  /* 0=> Off, 1=> Enabled */
00634 #define FE_MASK_LOAD_ENABLE_O           20  /* 0=> Off, 1=> Enabled */
00635 #define STATIC_BCID_ENABLE_O            21  /* 0=> Off, 1=> Enabled */
00636 #define STATIC_L1ID_ENABLE_O            22  /* 0=> Off, 1=> Enabled */
00637 #define CMB_DYN_MASK_RDY_O              23  /* self clearing */
00638 
00639 #define INPUT_FIFO_PLAY_INHIBIT_O       24
00640 
00641 #define FIFO_CTRL_MUX_O                 25 /* U FIFO (in, debug, event) MUX control */
00642 #define FIFO_CTRL_MUX_W                 1 /* U */
00643 #define FIFO_RESET                   0    /* U FIFO rst:debug FIFO block control */
00644 #define ROD_BUS_FIFO_ACCESS          1    /* U allows FIFO access over the ROD bus */
00645 
00646 #define DATA_PATH_SELECT_O              26 /* U data path mode selector */
00647 #define DATA_PATH_SELECT_W               2 /* U */
00648 #define TEST_BENCH_DATA_PATH          1    /* enable test bench data path */
00649 #define STANDARD_DATA_PATH            2    /* enable run time data path */
00650 
00651 #define ROD_TYPE_O                      31
00652 #define ROD_TYPE_SCT                0
00653 #define ROD_TYPE_PIXEL              1 
00654 
00655 /* RRIF_STATUS_1 */
00656 #define  TIM_CLK_OK_O         0  /* TRUE IS OK*/
00657 #define  BOC_CLK_OK_O         1  /* TRUE IS OK*/
00658 #define  BOC_BUSY_O           2  /*  TRUE IS BUSY */
00659 #define  CFG_READBACK_DONE_O  3
00660 #define  CAL_TEST_RDY_O       4
00661 #define  TRIG_FIFO_EF_O       5 
00662 #define  TRIG_FIFO_FF_O       6
00663 #define  RMB_FIFOA_EF_O       7  /* FORM MODEBIT FIFOA EMPTY FLAG */
00664 #define  RMB_FIFOA_FF_O       8  /* FORM MODEBIT FIFOA FULL FLAG */
00665 #define  RMB_FIFOB_EF_O       9  /* FORM MODE FULL FLAG,BIT 0 BANK A,BIT 1 BANK B */
00666 #define  RMB_FIFOB_FF_O       10 /* FULL IS TRUE */
00667 #define  HEADER_TRAIL_LMT_O   11 /* FORM TRAILER LIMIT,BIT 0 BANK A,BIT 1 BANK B*/
00668 #define  HEADER_TRAIL_LMT_W 2    /* LIMIT IS TRUE */
00669 #define  ROD_BUSY_O           13 /* ROD BUSY,BIT 0 BANK A, BIT 1 BANK B */
00670 #define  ROD_BUSY_W         2    /* BUSY IS TRUE */
00671 #define  DM_FIFO_EF_O         15 /* DYN MASK FIFO EMPTY FLAG, EMPTY IS TRUE */
00672 #define  DM_FIFO_FF_O         16 /* DYN MASK FIFO FULL FLAG, FULL IS TRUE */
00673 #define  EFB_EV_ID_EMP_ERR_O  17 /* EFB EVENT EMPTY FLAG, ERROR IS TRUE 
00674                                     (FORMATTER PLAYS DATA BEFORE ID IN EFB) */
00675 #define  EVT_MEM_A_EMP_O      18 /* EVENT MEMORY A EMPTY, EMPTY IS TRUE */
00676 #define  EVT_MEM_A_FULL_O     19 /* EVENT MEMORY A FULL, FULL IS TRUE */
00677 #define  EVT_MEM_B_EMP_O      20 /* EVENT MEMORY B EMPTY, EMPTY IS TRUE */
00678 #define  EVT_MEM_B_FULL_O     21 /* EVENT MEMORY B FULL, FULL IS TRUE */
00679 #define  FE_CMD_PULSE_CNT_O   22 /* CNT # TRIG DATA,IT HAS NOT SENT TO FORMATTERS */
00680 #define  FE_CMD_PULSE_CNT_W    8
00681 #define  FE_OCC_CNTRS_EF_O    30 /* TRUE IF ALL FRONT END COUNTER ARE ZERO */
00682 #define  MODE_BITS_ERR        31 
00683 
00684 /* RRIF_STATUS_O */
00685 #define  RS0_ROD_TYPE_O           31 
00686 #define  RS0_DSP_PRESENT_O(slv)   (27 +slv) 
00687 
00688 /* FE_CMND_MASK_LO     */ 
00689 #define  FE_CMD_MASK_LO_O      0 /* COMMAND MASK 0 FOR LINKS 0(BIT 0) TO 31 */
00690 #define  FE_CMD_MASK_LO_W     32
00691 
00692 /* FE_CMND_MASK_HI     */
00693 #define  FE_CMD_MASK_HI_O      0 /* COMMAND MASK 0 FOR LINKS 32(BIT 0) TO 47(BIT 15)*/
00694 #define  FE_CMD_MASK_HI_W     16
00695 
00696 /* CALSTROBE_DELAY       */
00697 #define  CALSTROBE_DELAY_O     0 /* DELAY IN CLK40 TICK FROM TEST PULSE TO TRIG GEN*/
00698 #define  CALSTROBE_DELAY_W     6
00699 
00700 /* CAL_CMND              */
00701 #define  CAL_CMD_O             0 /* REG THAT IS SHIFTED OUT SERIAL ON COMD ???*/
00702 #define  CAL_CMD_W            26
00703 
00704 /* FRMT_RMB_STATUS    */
00705 #define  MB_FIFO_A_EMP_O       0
00706 #define  MB_FIFO_A_FULL_O      1
00707 #define  MB_FIFO_A_WC_O        2
00708 #define  MB_FIFO_A_WC_W        8
00709                            /* 10 TO 15 NOT USED  */
00710 #define  MB_FIFO_B_EMP_O      16
00711 #define  MB_FIFO_B_FULL_O     17
00712 #define  MB_FIFO_B_WC_O       18
00713 #define  MB_FIFO_B_WC_W        8 
00714                            /* 26 TO 31 NOT USED */ 
00715 
00716 /* EFB_DM_FIFO_FLAG_STA  */
00717 #define  L1ID_BCID_FIFO_EMP_O            0  /*L1 & BC ID FIFO EMPTY, EMPTY IS TRUE*/
00718 #define  TRIG_TYP_FIFO_EMP_O             1  /*TRIG TYP FROM TIM FIFO EMP. EMP IS TRUE*/
00719 #define  L1ID_BCID_TT_FIFO_EMP_O         2  /*FIFO OF ABOVE 21 FIFO EMP. EMP IS TRUE*/
00720 #define  DEFAULT_DYN_MASK_FIFO_EMP_O     3  /*DYN MASK FIFO EMP, EMP IS TRUE*/
00721 #define  CORR_TRIG_DYN_MASK_FIFO_EMP_O   4  /*CORR DNT MASK FIFO EMP, EMP IS TRUE */
00722 //bits 5-7 not used.
00723 #define  L1ID_BCID_FIFO_FULL_O           8  /*L1 & BC ID FIFO FULL, FULL IS TRUE*/
00724 #define  TRIG_TYP_FIFO_FULL_O            9  /*TRIG TYP FROM TIM FIFO FULL. FULL IS TRUE*/
00725 #define  L1ID_BCID_TT_FIFO_FULL_O        10 /*FIFO OF ABOVE 21 FIFO FULL. FULL IS TRUE*/
00726 #define  DFLT_MASK_FIFO_FULL_O           11 /*DEFAULT DYN MASK FIFO FULL, FULL IS TRUE*/
00727 #define  CORR_TRIG_DYN_MASK_FIFO_FULL_O  12 /*CORR DYN MASK FIFO FULL, FULL IS TRUE */
00728 
00729 /* EFB_DM_WC_STA_REG     */                         
00730 #define  EVENT_ID_COUNT_O       0  /* WORD COUNT FOR EVENT ID FIFO  */
00731 #define  EVENT_ID_COUNT_W       6
00732 //bits 6-7 not used
00733 #define  EVENT_TRIG_COUNT_O     8  /* WORD COUNT FOR EVENT TRIG FIFO  */
00734 #define  EVENT_TRIG_COUNT_W     6
00735 //bits 14-15 not used
00736 #define  EVENT_MASK_COUNT_O    16  /* WORD COUNT FOR EVENT DYN MASK FIFO  */
00737 #define  EVENT_MASK_COUNT_W     6
00738 //bits 22-23 not used
00739 #define  EVENT_HEADER_COUNT_O  24  /* WORD COUNT FOR EVENT HEADER FIFO  */
00740 #define  EVENT_HEADER_COUNT_W   6
00741  
00742 /* INP_MEM_CTRL          */
00743 #define  INMEM_A_WC_O           0  /*INMEM A WC OR GEN PURPOSE DEBUG COUNTER */
00744 #define  INMEM_A_WC_W          16
00745 #define  INMEM_B_WC_O          16  /*INMEM B WC OR GEN PURPOSE DEBUG COUNTER */
00746 #define  INMEM_B_WC_W          16
00747 
00748 /* DBG_MEM_CTRL          */
00749 #define  DBGMEM_A_WC_O          0  /*DBGMEM A WC OR GEN PURPOSE DEBUG COUNTER */
00750 #define  DBGMEM_A_WC_W         16
00751 #define  DBGMEM_B_WC_O         16  /*DBGMEM B WC OR GEN PURPOSE DEBUG COUNTER */
00752 #define  DBGMEM_B_WC_W         16
00753 
00754 /* CFG_READBACK_CNT          */ 
00755 #define  FIFO_WRITE_CNT_O        0  /* FIFO writing time, in clock ticks. */
00756 #define  FIFO_WRITE_CNT_W        16
00757 #define  DELAY_FIFO_WRITE_O      16  /* Delay in ticks before the FIFO begins trapping data, */
00758 #define  DELAY_FIFO_WRITE_W      16  /* when the cfg readback bit is set in RRIF CMD 1 */
00759 
00760 /* IDE_MEM_CTRL          */
00761 #define  EN_INMEM_A_COUNT_O     0 /* ENABLE INPUT MEMORY A COUNTER */
00762 #define  LOAD_INMEM_A_COUNT_O   1 /* LOAD INPUT MEMORY A COUNTER */
00763 #define  EN_INMEM_B_COUNT_O     2 /* ENABLE INPUT MEMORY B COUNTER */
00764 #define  LOAD_INMEM_B_COUNT_O   3 /* LOAD INPUT MEMORY B COUNTER */
00765 #define  EN_DBGMEM_A_COUNT_O    4 /* ENABLE DEBUG MEMORY A COUNTER */
00766 #define  LOAD_DBGMEM_A_COUNT_O  5 /* LOAD DEBUG MEMORY A COUNTER */
00767 #define  EN_DBGMEM_B_COUNT_O    6 /* ENABLE DEBUG MEMORY B COUNTER */
00768 #define  LOAD_DBGMEM_B_COUNT_O  7 /* LOAD DEBUG MEMORY B COUNTER */
00769 #define  EN_EVTMEM_A_COUNT_O    8 /* ENABLE EVENT MEMORY A COUNTER */
00770 #define  LOAD_EVTMEM_A_COUNT_O  9 /* LOAD EVENT MEMORY A COUNTER */
00771 #define  EN_EVTMEM_B_COUNT_O   10 /* ENABLE EVENT MEMORY B COUNTER */
00772 #define  LOAD_EVTMEM_B_COUNT_O 11 /* LOAD EVENT MEMORY B COUNTER */
00773 #define TEST_FIXTURE_MODE_O    12 /* SELECTION OF TEST BENC MODES */
00774 #define TEST_FIXTURE_MODE_W     6 /* LIST OF MODES ????????      */
00775 
00776 /* IDE_MEM_STAT */
00777 #define INP_MEM_A_DONE_O                  0  /* IN MEM COUNTER, ZERO IS TRUE */
00778 #define INP_MEM_B_DONE_O                  1  /* IN MEM COUNTER, ZERO IS TRUE */
00779 #define DBG_MEM_A_DONE_O                  2  /* IN MEM COUNTER, ZERO IS TRUE */
00780 #define DBG_MEM_B_DONE_O                  3  /* IN MEM COUNTER, ZERO IS TRUE */
00781 #define CFG_READBACK_WRT_CNT_DONE_O       4
00782 #define CFG_READBACK_DELAY_CNT_DONE_O     5
00783 #define OPERATION_DONE_O                  6  /* TEST BENCH OPER COMPLETE, COMP IS TRUE*/
00784 #define MEM_OP_DONE_W                     2  /*  00 AND 11 IS ONLY VALUE USED */  
00785 #define INMEM_A_EMP_O                     8
00786 #define INMEM_A_FULL_O                    9
00787 #define INMEM_B_EMP_O                     10
00788 #define INMEM_B_FULL_O                    11
00789 #define DBGMEM_A_EMP_O                    12
00790 #define DBGMEM_A_FULL_O                   13
00791 #define DBGMEM_B_EMP_O                    14
00792 #define DBGMEM_B_FULL_O                   15
00793 #define TIM_FIFO_EF_O                     16  /*  INTERN TIM FIFO EMPTY, EMPTY IS TRUE*/
00794 #define TIM_FIFO_FF_O                     17  /*  INTERN TIM FIFO FULL, FULL IS TRUE*/
00795 #define TIM_FIFO_WC_O                     18  /*  INTERN TIM FIFO CURR WORD COUNT */ 
00796 #define TIM_FIFO_WC_W                     13  
00797 
00798 /* INTRPT_TO_SLV         */ 
00799 #define MASTER_TO_SLV_INT_O    0  /* MASTER TO SLAVE HPI INT,BIT 0 IS SLAVE 1,*/ 
00800 #define MASTER_TO_SLV_INT_W    4  /* BIT 3 IS SLAVE 4 ??????? */
00801 
00802 /* INTRPT_FROM_SLV       */
00803 #define SLAVE_TO_MAST_INT_O    0
00804 #define SLAVE_TO_MAST_INT_W    4
00805 
00806 /* FE_OCC_CNTR_RESET(msk) */
00807 #define FE_OCC_CNTR_RST_O      0  /* RESET FOR 32 LINKS */
00808 #define FE_OCC_CNTR_RST_W     32
00809 
00810 /* FE_OCC_CNTR_LOAD(msk) */
00811 #define FE_OCC_CNTR_LOAD_O     0  /* LOAD FOR 32 LINKS */
00812 #define FE_OCC_CNTR_LOAD_W    32
00813 
00814 /* FE_OCC_LOAD_VALUE     */
00815 #define FE_OCC_LOAD_VAL_O      0  /* VALUE LOADED TO FE OCC COUNTERS */
00816 #define FE_OCC_LOAD_VAL_W      4
00817 
00818 /* DATA_LINK_MASK(msk)   */
00819 #define DATA_LINK_MASK_O       0
00820 #define DATA_LINK_MASK_W      32
00821 
00822 /* FE_OCC_CNTR(occ)     */
00823 #define  FE_OCC_CNTR_VAL_0_O    0
00824 #define  FE_OCC_CNTR_VAL_0_W    4
00825 #define  FE_OCC_CNTR_VAL_1_O    4
00826 #define  FE_OCC_CNTR_VAL_1_W    4
00827 #define  FE_OCC_CNTR_VAL_2_O    8
00828 #define  FE_OCC_CNTR_VAL_2_W    4
00829 #define  FE_OCC_CNTR_VAL_3_O   12
00830 #define  FE_OCC_CNTR_VAL_3_W    4
00831 #define  FE_OCC_CNTR_VAL_4_O   16
00832 #define  FE_OCC_CNTR_VAL_4_W    4
00833 #define  FE_OCC_CNTR_VAL_5_O   20
00834 #define  FE_OCC_CNTR_VAL_5_W    4
00835 #define  FE_OCC_CNTR_VAL_6_O   24
00836 #define  FE_OCC_CNTR_VAL_6_W    4
00837 #define  FE_OCC_CNTR_VAL_7_O   28
00838 #define  FE_OCC_CNTR_VAL_7_W    4
00839 
00840 /* RMB0_DFLT_LUT(fmt)    */
00841 #define  FMAT_MODE_BIT0_LINK_0_O    0
00842 #define  FMAT_MODE_BIT0_LINK_1_O    1
00843 #define  FMAT_MODE_BIT0_LINK_2_O    2
00844 #define  FMAT_MODE_BIT0_LINK_3_O    3
00845 #define  FMAT_MODE_BIT0_LINK_4_O    4
00846 #define  FMAT_MODE_BIT0_LINK_5_O    5
00847 #define  FMAT_MODE_BIT0_LINK_6_O    6
00848 #define  FMAT_MODE_BIT0_LINK_7_O    7
00849 #define  FMAT_MODE_BIT0_LINK_8_O    8
00850 #define  FMAT_MODE_BIT0_LINK_9_O    9
00851 #define  FMAT_MODE_BIT0_LINK_10_O  10
00852 #define  FMAT_MODE_BIT0_LINK_11_O  11
00853 #define  FMAT_MODE_BIT1_LINK_0_O    0
00854 #define  FMAT_MODE_BIT1_LINK_1_O    1
00855 #define  FMAT_MODE_BIT1_LINK_2_O    2
00856 #define  FMAT_MODE_BIT1_LINK_3_O    3
00857 #define  FMAT_MODE_BIT1_LINK_4_O    4
00858 #define  FMAT_MODE_BIT1_LINK_5_O    5
00859 #define  FMAT_MODE_BIT1_LINK_6_O    6
00860 #define  FMAT_MODE_BIT1_LINK_7_O    7
00861 #define  FMAT_MODE_BIT1_LINK_8_O    8
00862 #define  FMAT_MODE_BIT1_LINK_9_O    9
00863 #define  FMAT_MODE_BIT1_LINK_10_O  10
00864 #define  FMAT_MODE_BIT1_LINK_11_O  11
00865 
00866 /* RMB0&1_CRTV_LUT(fmt)    */
00867 #define  FMAT_CRTV_BIT0_LINK_0_O    0
00868 #define  FMAT_CRTV_BIT0_LINK_1_O    1
00869 #define  FMAT_CRTV_BIT0_LINK_2_O    2
00870 #define  FMAT_CRTV_BIT0_LINK_3_O    3
00871 #define  FMAT_CRTV_BIT0_LINK_4_O    4
00872 #define  FMAT_CRTV_BIT0_LINK_5_O    5
00873 #define  FMAT_CRTV_BIT0_LINK_6_O    6
00874 #define  FMAT_CRTV_BIT0_LINK_7_O    7
00875 #define  FMAT_CRTV_BIT0_LINK_8_O    8
00876 #define  FMAT_CRTV_BIT0_LINK_9_O    9
00877 #define  FMAT_CRTV_BIT0_LINK_10_O  10
00878 #define  FMAT_CRTV_BIT0_LINK_11_O  11
00879 #define  FMAT_CRTV_BIT1_LINK_0_O    0
00880 #define  FMAT_CRTV_BIT1_LINK_1_O    1
00881 #define  FMAT_CRTV_BIT1_LINK_2_O    2
00882 #define  FMAT_CRTV_BIT1_LINK_3_O    3
00883 #define  FMAT_CRTV_BIT1_LINK_4_O    4
00884 #define  FMAT_CRTV_BIT1_LINK_5_O    5
00885 #define  FMAT_CRTV_BIT1_LINK_6_O    6
00886 #define  FMAT_CRTV_BIT1_LINK_7_O    7
00887 #define  FMAT_CRTV_BIT1_LINK_8_O    8
00888 #define  FMAT_CRTV_BIT1_LINK_9_O    9
00889 #define  FMAT_CRTV_BIT1_LINK_10_O  10
00890 #define  FMAT_CRTV_BIT1_LINK_11_O  11
00891 
00892 /* DFLT_ROD_EVT_TYPE     */
00893 #define  DFLT_ROD_EVT_TYPE_O   0
00894 #define  DFLT_ROD_EVT_TYPE_W   16
00895 
00896 /* DM_DFLT_LUT(mbLut)    */
00897 #define  EFB_DF_DYN_MASK_BIT0_LNK0_O  0  /* WORD HAS SAME PAT FOR EACH LINK */
00898 #define  EFB_DF_DYN_MASK_BIT1_LNK0_O  1   
00899 #define  EFB_DF_DYN_MASK_BIT0_LNK1_O  2  
00900 #define  EFB_DF_DYN_MASK_BIT1_LNK1_O  3   
00901 #define  EFB_DF_DYN_MASK_BIT0_LNK2_O  4  
00902 #define  EFB_DF_DYN_MASK_BIT1_LNK2_O  5   
00903 #define  EFB_DF_DYN_MASK_BIT0_LNK3_O  6  
00904 #define  EFB_DF_DYN_MASK_BIT1_LNK3_O  7   
00905 #define  EFB_DF_DYN_MASK_BIT0_LNK4_O  8  
00906 #define  EFB_DF_DYN_MASK_BIT1_LNK4_O  9   
00907 #define  EFB_DF_DYN_MASK_BIT0_LNK5_O 10  
00908 #define  EFB_DF_DYN_MASK_BIT1_LNK5_O 11   
00909 #define  EFB_DF_DYN_MASK_BIT0_LNK6_O 12  
00910 #define  EFB_DF_DYN_MASK_BIT1_LNK6_O 13   
00911 #define  EFB_DF_DYN_MASK_BIT0_LNK7_O 14  
00912 #define  EFB_DF_DYN_MASK_BIT1_LNK7_O 15   
00913 
00914 /* CRTV_ROD_EVT_TYPE     */
00915 #define  CRTV_ROD_EVT_TYPE_O   0
00916 #define  CRTV_ROD_EVT_TYPE_W   16
00917 
00918 /* DM_CRTV_LUT(mbLut)    */
00919 #define  EFB_CR_DYN_MASK_BIT0_LNK0_O  0  /* WORD HAS SAME PAT FOR EACH LINK */
00920 #define  EFB_CR_DYN_MASK_BIT1_LNK0_O  1   
00921 #define  EFB_CR_DYN_MASK_BIT0_LNK1_O  2  
00922 #define  EFB_CR_DYN_MASK_BIT1_LNK1_O  3   
00923 #define  EFB_CR_DYN_MASK_BIT0_LNK2_O  4  
00924 #define  EFB_CR_DYN_MASK_BIT1_LNK2_O  5   
00925 #define  EFB_CR_DYN_MASK_BIT0_LNK3_O  6  
00926 #define  EFB_CR_DYN_MASK_BIT1_LNK3_O  7   
00927 #define  EFB_CR_DYN_MASK_BIT0_LNK4_O  8  
00928 #define  EFB_CR_DYN_MASK_BIT1_LNK4_O  9   
00929 #define  EFB_CR_DYN_MASK_BIT0_LNK5_O 10  
00930 #define  EFB_CR_DYN_MASK_BIT1_LNK5_O 11   
00931 #define  EFB_CR_DYN_MASK_BIT0_LNK6_O 12  
00932 #define  EFB_CR_DYN_MASK_BIT1_LNK6_O 13   
00933 #define  EFB_CR_DYN_MASK_BIT0_LNK7_O 14  
00934 #define  EFB_CR_DYN_MASK_BIT1_LNK7_O 15  
00935 
00936 /* CORRECTED_EVENTS_FIFO */
00937 #define  CRTV_EVNT_FIFO_O  0
00938 #define  CRTV_EVNT_FIFO_W 16
00939 
00940 /* CAL_L1_TRIG_TYPE */
00941 #define  CAL_L1_TRIG_TYPE_O     0
00942 #define  CAL_L1_TRIG_TYPE_W    10
00943 /* CAL_L1_ID */
00944 #define  CAL_L1_ID_O            0
00945 #define  CAL_L1_ID_W           24
00946 
00947 #endif

Generated on Thu Dec 15 21:14:32 2005 for SCT DAQ/DCS Software - C++ by doxygen 1.3.5