00001
00002
00003 #ifndef SCTPIXELROD_TIMDEFINE_H
00004 #define SCTPIXELROD_TIMDEFINE_H
00005
00034 namespace SctPixelRod {
00035
00036 #include "processor.h"
00037
00039
00040 enum TimTimingSCT {
00041 TIM_L1A_DEADTIME = 3,
00042 TIM_ECR_DEADTIME = 7,
00043 TIM_BCR_DEADTIME = 7,
00044 TIM_CAL_DEADTIME = 27,
00045 TIM_BCID_OFFSET = 6
00046 };
00047
00048 const INT32 TIM_L1ID_FIRST = 0;
00049
00053 const INT32 TIM_SEQ_SIZE = 0x4000;
00054 const INT32 TIM_SEQ_ADDR = 0x8000;
00055
00057
00058 enum TimRegister {
00059 TIM_REG_ENABLES = 0x00,
00060 TIM_REG_COMMAND = 0x02,
00061 TIM_REG_BURST_COUNT = 0x04,
00062 TIM_REG_FREQUENCY = 0x06,
00063 TIM_REG_WINDOW = 0x08,
00064 TIM_REG_DELAY = 0x0A,
00065 TIM_REG_STATUS = 0x0C,
00066 TIM_REG_FIFO_STATUS = 0x0E,
00067 TIM_REG_TRIGGER_IDLO = 0x10,
00068 TIM_REG_TRIGGER_IDHI = 0x12,
00069 TIM_REG_TRIGGER_BCID = 0x14,
00070 TIM_REG_TRIGGER_TYPE = 0x16,
00071 TIM_REG_RUN_ENABLES = 0x18,
00072 TIM_REG_SEQ_CONTROL = 0x1A,
00073 TIM_REG_SEQ_END = 0x1C,
00074 TIM_REG_ROD_MASK = 0x1E,
00075 TIM_REG_ROD_BUSY = 0x20,
00076 TIM_REG_ROD_LATCH = 0x22,
00077 TIM_REG_ROD_MONITOR = 0x24,
00078 TIM_REG_TTC_DATA = 0x26,
00079 TIM_REG_TTC_SELECT = 0x28,
00080 TIM_REG_TTC_BCID = 0x2A,
00081 TIM_REG_TTC_RX = 0x2C,
00082 TIM_REG_TTC_STATUS = 0x2E,
00083 TIM_REG_OUTPUT = 0x30,
00084 TIM_REG_TIM_ID = 0x32,
00085
00086 TIM_REG_STATUS3 = 0x4A,
00087 TIM_REG_DEBUG_CTL = 0x9C
00088 };
00089
00091
00092 enum TimBitEnables {
00093 TIM_BIT_EN_INT_TRIG = 0x0002,
00094 TIM_BIT_EN_INT_ECR = 0x0004,
00095 TIM_BIT_EN_INT_BCR = 0x0008,
00096 TIM_BIT_EN_RANDOM = 0x0010,
00097 TIM_BIT_EN_INT_FER = 0x0020,
00098 TIM_BIT_EN_WINDOW = 0x0040,
00099 TIM_BIT_EN_INT_BUSY = 0x0080,
00100
00101 TIM_BIT_EN_EXT_CLK = 0x0100,
00102 TIM_BIT_EN_EXT_TRIG = 0x0200,
00103 TIM_BIT_EN_EXT_ECR = 0x0400,
00104 TIM_BIT_EN_EXT_BCR = 0x0800,
00105 TIM_BIT_EN_EXT_CAL = 0x1000,
00106 TIM_BIT_EN_EXT_FER = 0x2000,
00107 TIM_BIT_EN_EXT_SEQ = 0x4000,
00108 TIM_BIT_EN_EXT_BUSY = 0x8000
00109 };
00110
00112 enum TimBitBackplane {
00113 TIM_L1A = 0x01,
00114 TIM_ECR = 0x02,
00115 TIM_BCR = 0x04,
00116 TIM_CAL = 0x08,
00117 TIM_SID = 0x10,
00118 TIM_STT = 0x20,
00119 TIM_CMD = 0xCF,
00120 TIM_RES = 0xC0,
00121 TIM_FER = 0x40,
00122 TIM_SPA = 0x80,
00123 TIM_TRG = 0x31
00124 };
00126 enum TimBitCommand {
00127 TIM_VTRG = 0x02,
00128 TIM_VECR = 0x04,
00129 TIM_VBCR = 0x08,
00130 TIM_VCAL = 0x10,
00131 TIM_VFER = 0x20,
00132 TIM_VSPA = 0x40,
00133
00134 TIM_BIT_EN_TTC = 0x1000,
00135 TIM_BIT_VRESET = 0x8000
00136 };
00137
00138 enum TimBitRunEnables {
00139 TIM_BIT_EN_ID = 0x0200,
00140 TIM_BIT_EN_TYPE = 0x0400
00141 };
00142
00143 enum TimBitSeqControl {
00144 TIM_BIT_SEQ_EN_ALL = 0x00FF,
00145 TIM_BIT_SEQ_RESET = 0x0200,
00146 TIM_BIT_SEQ_GO = 0x0400,
00147 TIM_BIT_EN_CYCLIC = 0x0800
00148 };
00149
00150 enum TimBitTTCStatus {
00151 TIM_BIT_TTC_READY = 0x4000
00152 };
00154
00155 enum TimBitStatus3 {
00156 TIM_BIT_STATUS3_TTCCLKENOK = 0x0080,
00157 TIM_BIT_STATUS3_EXTCLKENOK = 0x0100,
00158 TIM_BIT_STATUS3_INTCLKENOK = 0x0200,
00159 TIM_BIT_STATUS3_PLLSTABLE = 0x0400
00160 };
00161
00162 enum TimBitDebugCtl {
00163 TIM_BIT_DEBUGCTL_CSBDISABLE = 0x0100,
00164 TIM_BIT_DEBUGCTL_FVDISABLE = 0x1000
00165 };
00166
00168
00170
00171 enum TimMaskFrequency {
00172 TIM_MASK_TRIG_600_KHZ = 0x0000,
00173 TIM_MASK_TRIG_300_KHZ = 0x0002,
00174 TIM_MASK_TRIG_200_KHZ = 0x0003,
00175 TIM_MASK_TRIG_150_KHZ = 0x0004,
00176 TIM_MASK_TRIG_120_KHZ = 0x0005,
00177 TIM_MASK_TRIG_100_KHZ = 0x0006,
00178 TIM_MASK_TRIG_60_0KHZ = 0x0001,
00179 TIM_MASK_TRIG_50_0KHZ = 0x0007,
00180 TIM_MASK_TRIG_30_0KHZ = 0x000A,
00181 TIM_MASK_TRIG_20_0KHZ = 0x000B,
00182 TIM_MASK_TRIG_15_0KHZ = 0x000C,
00183 TIM_MASK_TRIG_12_0KHZ = 0x000D,
00184 TIM_MASK_TRIG_10_0KHZ = 0x000E,
00185 TIM_MASK_TRIG_6_00KHZ = 0x0009,
00186 TIM_MASK_TRIG_5_00KHZ = 0x000F,
00187 TIM_MASK_TRIG_3_00KHZ = 0x0012,
00188 TIM_MASK_TRIG_2_00KHZ = 0x0013,
00189 TIM_MASK_TRIG_1_50KHZ = 0x0014,
00190 TIM_MASK_TRIG_1_20KHZ = 0x0015,
00191 TIM_MASK_TRIG_1_00KHZ = 0x0016,
00192 TIM_MASK_TRIG_0_60KHZ = 0x0011,
00193 TIM_MASK_TRIG_0_50KHZ = 0x0017,
00194 TIM_MASK_TRIG_0_30KHZ = 0x001A,
00195 TIM_MASK_TRIG_0_20KHZ = 0x001B,
00196 TIM_MASK_TRIG_0_15KHZ = 0x001C,
00197 TIM_MASK_TRIG_0_12KHZ = 0x001D,
00198 TIM_MASK_TRIG_0_10KHZ = 0x001E,
00199 TIM_MASK_TRIG_0_06KHZ = 0x0019,
00200 TIM_MASK_TRIG_0_05KHZ = 0x001F,
00201
00202 TIM_MASK_FECR_60_00HZ = 0x0000,
00203 TIM_MASK_FECR_30_00HZ = 0x0200,
00204 TIM_MASK_FECR_20_00HZ = 0x0300,
00205 TIM_MASK_FECR_15_00HZ = 0x0400,
00206 TIM_MASK_FECR_12_00HZ = 0x0500,
00207 TIM_MASK_FECR_10_00HZ = 0x0600,
00208 TIM_MASK_FECR_6_000HZ = 0x0100,
00209 TIM_MASK_FECR_5_000HZ = 0x0700,
00210 TIM_MASK_FECR_3_000HZ = 0x0A00,
00211 TIM_MASK_FECR_2_000HZ = 0x0B00,
00212 TIM_MASK_FECR_1_500HZ = 0x0C00,
00213 TIM_MASK_FECR_1_200HZ = 0x0D00,
00214 TIM_MASK_FECR_1_000HZ = 0x0E00,
00215 TIM_MASK_FECR_0_600HZ = 0x0900,
00216 TIM_MASK_FECR_0_500HZ = 0x0F00,
00217 TIM_MASK_FECR_0_300HZ = 0x1200,
00218 TIM_MASK_FECR_0_200HZ = 0x1300,
00219 TIM_MASK_FECR_0_150HZ = 0x1400,
00220 TIM_MASK_FECR_0_120HZ = 0x1500,
00221 TIM_MASK_FECR_0_100HZ = 0x1600,
00222 TIM_MASK_FECR_0_060HZ = 0x1100,
00223 TIM_MASK_FECR_0_050HZ = 0x1700,
00224 TIM_MASK_FECR_0_030HZ = 0x1A00,
00225 TIM_MASK_FECR_0_020HZ = 0x1B00,
00226 TIM_MASK_FECR_0_015HZ = 0x1C00,
00227 TIM_MASK_FECR_0_012HZ = 0x1D00,
00228 TIM_MASK_FECR_0_010HZ = 0x1E00,
00229 TIM_MASK_FECR_0_006HZ = 0x1900,
00230 TIM_MASK_FECR_0_005HZ = 0x1F00
00231 };
00232
00233 const int TIM_FREQ_SIZE = 29;
00234
00235 const int TIM_TRIG_FREQUENCY[TIM_FREQ_SIZE][2] = {
00236 { TIM_MASK_TRIG_600_KHZ, 600000 },
00237 { TIM_MASK_TRIG_300_KHZ, 300000 },
00238 { TIM_MASK_TRIG_200_KHZ, 200000 },
00239 { TIM_MASK_TRIG_150_KHZ, 150000 },
00240 { TIM_MASK_TRIG_120_KHZ, 120000 },
00241 { TIM_MASK_TRIG_100_KHZ, 100000 },
00242 { TIM_MASK_TRIG_60_0KHZ, 60000 },
00243 { TIM_MASK_TRIG_50_0KHZ, 50000 },
00244 { TIM_MASK_TRIG_30_0KHZ, 30000 },
00245 { TIM_MASK_TRIG_20_0KHZ, 20000 },
00246 { TIM_MASK_TRIG_15_0KHZ, 15000 },
00247 { TIM_MASK_TRIG_12_0KHZ, 12000 },
00248 { TIM_MASK_TRIG_10_0KHZ, 10000 },
00249 { TIM_MASK_TRIG_6_00KHZ, 6000 },
00250 { TIM_MASK_TRIG_5_00KHZ, 5000 },
00251 { TIM_MASK_TRIG_3_00KHZ, 3000 },
00252 { TIM_MASK_TRIG_2_00KHZ, 2000 },
00253 { TIM_MASK_TRIG_1_50KHZ, 1500 },
00254 { TIM_MASK_TRIG_1_20KHZ, 1200 },
00255 { TIM_MASK_TRIG_1_00KHZ, 1000 },
00256 { TIM_MASK_TRIG_0_60KHZ, 600 },
00257 { TIM_MASK_TRIG_0_50KHZ, 500 },
00258 { TIM_MASK_TRIG_0_30KHZ, 300 },
00259 { TIM_MASK_TRIG_0_20KHZ, 200 },
00260 { TIM_MASK_TRIG_0_15KHZ, 150 },
00261 { TIM_MASK_TRIG_0_12KHZ, 120 },
00262 { TIM_MASK_TRIG_0_10KHZ, 100 },
00263 { TIM_MASK_TRIG_0_06KHZ, 60 },
00264 { TIM_MASK_TRIG_0_05KHZ, 50 }
00265 };
00266
00267 const int TIM_FECR_FREQUENCY[TIM_FREQ_SIZE][2] = {
00268 { TIM_MASK_FECR_60_00HZ, 60000 },
00269 { TIM_MASK_FECR_30_00HZ, 30000 },
00270 { TIM_MASK_FECR_20_00HZ, 20000 },
00271 { TIM_MASK_FECR_15_00HZ, 15000 },
00272 { TIM_MASK_FECR_12_00HZ, 12000 },
00273 { TIM_MASK_FECR_10_00HZ, 10000 },
00274 { TIM_MASK_FECR_6_000HZ, 6000 },
00275 { TIM_MASK_FECR_5_000HZ, 5000 },
00276 { TIM_MASK_FECR_3_000HZ, 3000 },
00277 { TIM_MASK_FECR_2_000HZ, 2000 },
00278 { TIM_MASK_FECR_1_500HZ, 1500 },
00279 { TIM_MASK_FECR_1_200HZ, 1200 },
00280 { TIM_MASK_FECR_1_000HZ, 1000 },
00281 { TIM_MASK_FECR_0_600HZ, 600 },
00282 { TIM_MASK_FECR_0_500HZ, 500 },
00283 { TIM_MASK_FECR_0_300HZ, 300 },
00284 { TIM_MASK_FECR_0_200HZ, 200 },
00285 { TIM_MASK_FECR_0_150HZ, 150 },
00286 { TIM_MASK_FECR_0_120HZ, 120 },
00287 { TIM_MASK_FECR_0_100HZ, 100 },
00288 { TIM_MASK_FECR_0_060HZ, 60 },
00289 { TIM_MASK_FECR_0_050HZ, 50 },
00290 { TIM_MASK_FECR_0_030HZ, 30 },
00291 { TIM_MASK_FECR_0_020HZ, 20 },
00292 { TIM_MASK_FECR_0_015HZ, 15 },
00293 { TIM_MASK_FECR_0_012HZ, 12 },
00294 { TIM_MASK_FECR_0_010HZ, 10 },
00295 { TIM_MASK_FECR_0_006HZ, 6 },
00296 { TIM_MASK_FECR_0_005HZ, 5 }
00297 };
00298
00299 }
00300
00301 #endif // SCTPIXELROD_TIMDEFINE_H