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BocAddresses.h

00001 //File: BocAddresses.h
00002 
00003 #ifndef SCTPIXELROD_BOCADDRESSES_H
00004 #define SCTPIXELROD_BOCADDRESSES_H
00005 
00018 #include "../CommonWithDsp/processor.h"
00019 #include "../CommonWithDsp/memoryPartitions.h"
00020 
00021 namespace SctPixelRod {
00022 
00023 // Use only the names in this file in C++ code.
00024 
00025 //Get the BOC base address from the testBench definitions.
00026 //CE0_BASE is the start of the window for RRIF registers
00027 //Unfortunately, memoryPartitions.h does not define the BOC
00028 //offset from this base in an available form.
00029 
00030 const unsigned long BOC_ADDRESS_BASE =         CE0_BASE + 0x8000;
00031 
00032 const unsigned long BOC_ADDRESS_WINDOW =       0x1000;
00033 
00034 // Default width for BOC registers. Registers with smaller range
00035 // are defined explicitly below.
00036 const unsigned long BOC_REGISTER_WIDTH =       8;
00037 
00038 //The following addresses are offsets from BOC_ADDRESS_BASE for BOC1
00039 
00040 //Start with the BPM12 chips - base for channel 0
00041 const unsigned long BOC_BPM_BASE =             0x000;
00042 
00043 //Offsets within BPM12 for individual channel functions
00044 enum bocBpmRegisters {
00045     BOC_BPM_INHIBIT =        0x0,
00046     BOC_BPM_MARK_SPACE =     0x4,
00047     BOC_BPM_COARSE =         0x8,
00048     BOC_BPM_FINE =           0xC
00049 };
00050 const unsigned long BOC_BPM_INHIBIT_WIDTH =    1;
00051 const unsigned long BOC_BPM_MARK_SPACE_WIDTH = 5;
00052 const unsigned long BOC_BPM_COARSE_WIDTH =     5;
00053 const unsigned long BOC_BPM_FINE_WIDTH =       7;
00054 
00055 //Start addresses for other "blocks" 
00056 const unsigned long BOC_LASER_DAC =            0x600;
00057 const unsigned long BOC_DATA_DELAY =           0x800;
00058 const unsigned long BOC_DATA_DELAY_WIDTH =     5;
00059 const unsigned long BOC_STROBE_DELAY =         0xA00;
00060 const unsigned long BOC_STROBE_DELAY_WIDTH =   5;
00061 const unsigned long BOC_THRESHOLD_DAC =        0xC00;
00062 
00063 //Channel counts (useful for Pixels??)
00064 const unsigned long BOC_TRANSMIT_CHANNELS =    48;
00065 const unsigned long BOC_RECEIVE_CHANNELS =     96;
00066 const unsigned long BOC_STROBE_CHANNELS =      26;
00067 
00068 //The following addresses are for single registers.
00069 const unsigned long BOC_BPM_CLK_PHASE =        0x980;
00070 const unsigned long BOC_BREG_CLK_PHASE =       0x98C;
00071 const unsigned long BOC_VERNIER_CLK0_PHASE =   0x990;
00072 const unsigned long BOC_VERNIER_CLK0_WIDTH =   5;
00073 const unsigned long BOC_VERNIER_CLK1_PHASE =   0x994;
00074 const unsigned long BOC_VERNIER_CLK1_WIDTH =   5;
00075 
00076 const unsigned long BOC_VERNIER_CLK_MAXIMUM =  48;
00077 
00078 const unsigned long BOC_RESET =                0xF00;
00079 const unsigned long BOC_BPM_RESET =            0xF04;
00080 const unsigned long BOC_TXDAC_CLEAR =          0xF08;
00081 const unsigned long BOC_RXDAC_CLEAR =          0xF0C;
00082 
00083 // For series BOCs, all resets are on BOC_RESET as
00084 // individual bits. Also more resets are defined.
00085 enum boc_reset_bits {
00086     BOC_OK_RESET_BIT = 3,
00087     BOC_VPIN_RESET_BIT = 4,
00088     BOC_RXDAC_CLEAR_BIT = 5,
00089     BOC_TXDAC_CLEAR_BIT = 6,
00090     BOC_BPM_RESET_BIT = 7
00091 };
00092 
00093 const unsigned long BOC_STATUS =               0xF10;
00094 
00095 // The meanings of the BOC_STATUS bits are different for
00096 // pre-production and production BOCs. Some bits are
00097 // not used.
00098 enum boc_pre_production_status_bits {
00099     BOC_PRE_PRODUCTION_SW1 = 0,
00100     BOC_PRE_PRODUCTION_SW4 = 1,
00101     BOC_PRE_PRODUCTION_SW5 = 2,
00102     BOC_PRE_PRODUCTION_SW6 = 3,
00103     BOC_PRE_PRODUCTION_RODSENSE = 5,
00104     BOC_PRE_PRODUCTION_LOCLASEN = 6,
00105     BOC_PRE_PRODUCTION_REMLASEN = 7
00106 };
00107 //
00108 enum boc_production_status_bits {
00109     BOC_PRODUCTION_BOCOK = 1,
00110         BOC_PRODUCTION_VBOK = 2,
00111         BOC_PRODUCTION_VAOK = 3,
00112         BOC_PRODUCTION_ERRFLAG = 4,
00113         BOC_PRODUCTION_RODSENSE = 5,
00114         BOC_PRODUCTION_LOCLASEN= 6,
00115         BOC_PRODUCTION_REMLASEN = 7
00116 };
00117 
00118 const unsigned long BOC_RX_DATA_MODE =         0xF14;
00119 const unsigned long BOC_RX_DATA_MODE_WIDTH =   3;
00120 // Define the Rx Data mode register values
00121 // NB - not bits!!
00122 enum boc_rx_data_mode_values {
00123     BOC_RX_DATA_MODE_NORMAL = 0,
00124     BOC_RX_DATA_MODE_TIMING = 1,
00125     BOC_RX_DATA_MODE_PIXEL2 = 2,
00126     BOC_RX_DATA_MODE_PIXEL1 = 3,
00127     BOC_RX_DATA_MODE_CLOCK = 6,
00128     BOC_RX_DATA_MODE_TRANSPARENT = 7
00129 };
00130 const unsigned long BOC_VERNIER_FINE_PHASE =   0xF20;
00131 const unsigned long BOC_CLK_CONTROL =          0xF28;
00132 //Maximum width of series Clock Control register. Pre-production
00133 //BOCs have the register 2 bits smaller, Rev A/Rev B series
00134 //BOCs don't implement the most significant bit.
00135 const unsigned long BOC_CLK_CONTROL_WIDTH  =   6;
00136 // Define the clock control bits
00137 enum boc_clk_control_bits {
00138     BOC_CLOCK_INVERT = 0,
00139     BOC_CLOCK_HALF = 1,
00140     BOC_CLOCK_VERNIER_BYPASS = 2,
00141     BOC_CLOCK_BPMPH_BYPASS = 3,
00142     BOC_CLOCK_PHOS4_FIX = 4,
00143 //Rev C series BOC only
00144     BOC_CLOCK_HALF_INHIBIT = 5
00145 };
00146 
00147 const unsigned long BOC_FW_REV =               0xF40;
00148 const unsigned long BOC_HW_REV =               0xF44;
00149 const unsigned long BOC_MODULE_TYPE =          0xF48;
00150 const unsigned long BOC_MANUFACTURER =         0xF4C;
00151 const unsigned long BOC_SERIAL_NUMBER =        0xF60;
00152 
00153 //Monitor ADC is new for the series BOCs. Details are different
00154 //for the Rev A, B or C boards.
00155 // Also there are potentially versions of the boards with 10
00156 // or 12-bit ADCs.
00157 
00158 const unsigned long BOC_ADC_SETUP =            0xE00;
00159 const unsigned long BOC_ADC_CONFIG =           0xE04;
00160 const unsigned long BOC_ADC_CONVERT =          0xE08;
00161 const unsigned long BOC_ADC_LSB =              0xE10;
00162 const unsigned long BOC_ADC_MSB =              0xE14;
00163 const unsigned long BOC_ADC_MSB_WIDTH[2] =     {2 ,4};
00164 
00165 const unsigned long BOC_MONITOR_CHANNELS =     12;
00166 
00167 //BOC_BUSY_0 is bit 2 of RRIF_STATUS_1. I can't find the definition of
00168 //this register anywhere, so put it here for now.
00169 //This is now defined as an index elsewhere. Until I decide how to map
00170 //the index to a real address, the name below has changed.
00171 
00172 const unsigned long RRIF_STATUS_1_ADDRESS =    CE0_BASE + 0x4420;
00173 enum rrif_status_1_bits {
00174     BOC_BUSY_0 =        0x4
00175 };
00176 
00177 }; //  End namespace SctPixelRod
00178 
00179 #endif //SCTPIXELROD_BOCADDRESSES_H

Generated on Fri Sep 16 18:01:48 2005 for SCT DAQ/DCS Software - C++ by doxygen 1.3.5